JAJSCA1A June 2016 – September 2016 TPS3779-Q1 , TPS3780-Q1
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TPS3779-Q1 and TPS3780-Q1 are used as precision, dual-voltage detectors. The monitored voltage, VDD voltage, and output pullup voltage (TPS3780-Q1 only) can be independent voltages or connected in any configuration.
Threshold overdrive is how much VSENSE1 or VSENSE2 exceeds the specified threshold, and is important to know because a smaller overdrive results in a slower OUTx response. Threshold overdrive is calculated as a percent of the threshold in question, as shown in Equation 1:
where
Figure 16 illustrates the minimum detectable pulse on the SENSEx inputs versus overdrive, and is used to visualize the relationship that overdrive has on tPD(f) for negative-going events.
The resistor divider values and target threshold voltage can be calculated by using Equation 2 and Equation 3 to determine VMON(UV) and VMON(PG), respectively.
where
Choose RTOTAL (equal to R1 + R2) so that the current through the divider is approximately 100 times higher than the input current at the SENSEx pins. The resistors can have high values to minimize current consumption as a result of low input bias current without adding significant error to the resistive divider. For details on sizing input resistors, see the Optimizing Resistor Dividers at a Comparator Input application report (SLVA450), available for download from www.ti.com.
PARAMETER | DESIGN REQUIREMENT | DESIGN RESULT |
---|---|---|
VDD | 5 V | 5 V |
Hysteresis | 10% | 10% |
Monitored voltage 1 | 3.3 V nominal, VMON(PG) = 2.9 V, VMON(UV) = 2.6 V | VMON(PG) = 2.908 V, VMON(UV) = 2.618 V |
Monitored voltage 2 | 3 V nominal, VMON(PG) = 2.6 V, VMON(UV) = 2.4 V | VMON(PG) = 2.606 V, VMON(UV) = 2.371 V |
Output logic voltage | 3.3-V CMOS | 3.3-V CMOS |
PARAMETER | DESIGN REQUIREMENT | DESIGN RESULT |
---|---|---|
VDD | VMON | VMON |
Hysteresis | 10% | 10% |
Monitored voltage 1 | VMON(PG) = 3.3 V, VMON(UV) = 3 V | VMON(PG) = 3.330 V, VMON(UV) = 2.997 V |
Monitored voltage 2 | VMON(PG) = 3.9 V, VMON(UV) = 3.5 V | VMON(PG) = 3.921 V, VMON(UV) = 3.529 V |
where
where