JAJSCT5A March 2016 – May 2016 TPS3890
Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a 0.1-µF ceramic capacitor near the VDD pin. If a capacitor is not connected to the CT pin, then minimize parasitic capacitance on this pin so the RESET delay time is not adversely affected.
The layout example in shows how the TPS3890 is laid out on a printed circuit board (PCB) with a user-defined delay.