JAJSGR0F December   2010  – December 2018 TPS51916

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     アプリケーション概略
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VDDQ Switch Mode Power Supply Control
      2. 8.3.2  VREF and REFIN, VDDQ Output Voltage
      3. 8.3.3  Soft-Start and Powergood
      4. 8.3.4  Power State Control
      5. 8.3.5  Discharge Control
      6. 8.3.6  VTT and VTTREF
      7. 8.3.7  VDDQ Overvoltage and Undervoltage Protection
      8. 8.3.8  VDDQ Out-of-Bound Operation
      9. 8.3.9  VDDQ Overcurrent Protection
      10. 8.3.10 VTT Overcurrent Protection
      11. 8.3.11 V5IN Undervoltage Lockout Protection
      12. 8.3.12 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 MODE Pin Configuration
      2. 8.4.2 D-CAP™ Mode
    5. 8.5 D-CAP2™ Mode Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 DDR3, D-CAP™ 400-kHz Application with Tracking Discharge
        1. 9.1.1.1 Design Requirements
        2. 9.1.1.2 Detailed Design Procedure
          1. 9.1.1.2.1 1. Determine the value of R1 AND R2
          2. 9.1.1.2.2 2. Choose the inductor
          3. 9.1.1.2.3 3. Choose the OCL setting resistance, RTRIP
          4. 9.1.1.2.4 Choose the output capacitors
        3. 9.1.1.3 Application Curves
      2. 9.1.2 DDR3, DCAP-2 500-kHz Application, with Tracking Discharge
        1. 9.1.2.1 Design Requirements
        2. 9.1.2.2 Detailed Design Procedure
          1. 9.1.2.2.1 Select Mode and Switching Frequency
          2. 9.1.2.2.2 Determine output capacitance
        3. 9.1.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 コミュニティ・リソース
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating free-air temperature range, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE= 0 V, VS3= VS5= 5 V (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SUPPLY CURRENT
IV5IN(S0) V5IN supply current, in S0 TA = 25°C, No load, VS3 = VS5 = 5 V 590 μA
IV5IN(S3) V5IN supply current, in S3 TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V 500 μA
IV5INSDN V5IN shutdown current TA = 25°C, No load, VS3 = VS5 = 0 V 1 μA
IVLDOIN(S0) VLDOIN supply current, in S0 TA = 25°C, No load, VS3 = VS5 = 5 V 5 μA
IVLDOIN(S3) VLDOIN supply current, in S3 TA = 25°C, No load, VS3 = 0 V, VS5 = 5 V 5 μA
IVLDOINSDN VLDOIN shutdown current TA = 25°C, No load, VS3 = VS5 = 0 V 5 μA
VREF OUTPUT
VVREF Output voltage IVREF = 30 μA, TA = 25°C 1.8000 V
0 μA ≤ IVREF <300 μA, TA = –10°C to 85°C 1.7856 1.8144
0 μA ≤ IVREF <300 μA, TA = –40°C to 85°C 1.7820 1.8180
IVREFOCL Current limit VVREF = 1.7 V 0.4 0.8 mA
VTTREF OUTPUT
VVTTREF Output voltage VVDDQSNS/2 V
VVTTREF Output voltage tolerance to VVDDQ |IVTTREF| <100 μA, 1.2 V ≤ VVDDQSNS ≤ 1.8 V 49.2% 50.8%
|IVTTREF| <10 mA, 1.2 V ≤ VVDDQSNS ≤ 1.8 V 49% 51%
IVTTREFOCLSRC Source current limit VVDDQSNS = 1.8 V, VVTTREF= 0 V 10 18 mA
IVTTREFOCLSNK Sink current limit VVDDQSNS = 1.8 V, VVTTREF = 1.8 V 10 17 mA
IVTTREFDIS VTTREF discharge current TA = 25°C, VS3 = VS5 = 0 V, VVTTREF = 0.5 V 0.8 1.3 mA
VTT OUTPUT
VVTT Output voltage VVTTREF V
VVTTTOL Output voltage tolerance to VTTREF |IVTT| ≤ 10 mA, 1.2 V ≤ VVDDQSNS ≤ 1.8 V, IVTTREF= 0 A –20 20 mV
|IVTT| ≤ 1 A, 1.2 ≤ VVDDQSNS ≤ 1.8 V, IVTTREF= 0 A –30 30
|IVTT| ≤ 2 A, 1.4 V ≤ VVDDQSNS ≤ 1.8 V, IVTTREF= 0 A –40 40
|IVTT| ≤ 1.5 A, 1.2 V ≤ VVDDQSNS ≤ 1.4 V, IVTTREF= 0 A –40 40
IVTTOCLSRC Source current limit VVDDQSNS = 1.8 V, VVTT = VVTTSNS = 0.7 V, IVTTREF= 0 A 2 3 A
IVTTOCLSNK Sink current limit VVDDQSNS = 1.8 V, VVTT = VVTTSNS = 1.1 V, IVTTREF= 0 A 2 3
IVTTLK Leakage current TA = 25°C , VS3 = 0 V, VS5 = 5 V, VVTT = VVTTREF 5 μA
IVTTSNSBIAS VTTSNS input bias current VS3 = 5 V, VS5 = 5 V, VVTTSNS = VVTTREF –0.5 0.0 0.5
IVTTSNSLK VTTSNS leakage current VS3 = 0 V, VS5 = 5 V, VVTTSNS = VVTTREF –1 0 1
IVTTDIS VTT Discharge current TA = 25°C, VS3 = VS5 = 0 V, VVDDQSNS = 1.8 V,
VVTT = 0.5 V, IVTTREF= 0 A		 7.8 mA
VDDQ OUTPUT
VVDDQSNS VDDQ sense voltage VREFIN
VVDDQSNSTOL VDDQSNS regulation voltage tolerance to REFIN TA = 25°C –3 3 mV
IVDDQSNS VDDQSNS input current VVDDQSNS = 1.8 V 39 μA
IREFIN REFIN input current VREFIN = 1.8 V –0.1 0.0 0.1 μA
IVDDQDIS VDDQ discharge current VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, MODE pin pulled down to GND through 47 kΩ (Non-tracking) 12 mA
IVLDOINDIS VLDOIN discharge current VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, MODE pin pulled down to GND through 100 kΩ (Tracking) 1.2 A
SWITCH MODE POWER SUPPLY (SMPS) FREQUENCY
fSW VDDQ switching frequency VIN = 12 V, VVDDQSNS = 1.8 V,
RMODE = 100 kΩ		 300 kHz
VIN = 12 V, VVDDQSNS = 1.8 V,
RMODE = 200 kΩ		 400
VIN = 12 V, VVDDQSNS = 1.8 V,
RMODE = 1 kΩ		 500
VIN = 12 V, VVDDQSNS = 1.8 V,
RMODE = 12 kΩ		 670
tON(min) Minimum on-time(1) DRVH rising to falling 60 ns
tOFF(min) Minimum off-time DRVH falling to rising 200 320 450
VDDQ MOSFET DRIVER
RDRVH DRVH resistance Source, IDRVH = –50 mA 1.6 3.0 Ω
Sink, IDRVH = 50 mA 0.6 1.5
RDRVL DRVL resistance Source, IDRVL = –50 mA 0.9 2.0
Sink, IDRVL = 50 mA 0.5 1.2
tDEAD Dead time DRVH-off to DRVL-on 10 ns
DRVL-off to DRVH-on 20
INTERNAL BOOT STRAP SW
VFBST Forward voltage VV5IN-VBST, TA = 25°C, IF = 10 mA 0.1 0.2 V
IVBSTLK VBST leakage current TA = 25°C, VVBST = 33 V, VSW = 28 V 0.01 1.5 μA
LOGIC THRESHOLD
IMODE MODE source current 14 15 16 μA
VTHMODE MODE threshold voltage MODE 0-1 109 129 149 mV
MODE 1-2 235 255 275
MODE 2-3 392 412 432
MODE 3-4 580 600 620
MODE 4-5 829 854 879
MODE 5-6 1202 1232 1262
MODE 6-7 1760 1800 1840
VIL S3 or S5 low-level voltage 0.5 V
VIH S3 or S5 high-level voltage 1.5
VIHYST S3 or S5 hysteresis voltage 0.25
IILK S3 or S5 input leak current –1 0 1 μA
SOFT START
tSS VDDQ soft-start time Internal soft-start time, CVREF = 0.1 μF,
S5 rising to VVDDQSNS > 0.99 × VREFIN 		1.1 ms
PGOOD COMPARATOR
VTHPG VDDQ PGOOD threshold PGOOD in from higher 106% 108% 110%
PGOOD in from lower 90% 92% 94%
PGOOD out to higher 114% 116% 118%
PGOOD out to lower 82% 84% 86%
IPG PGOOD sink current VPGOOD = 0.5 V 3 5.9 mA
tPGDLY PGOOD delay time Delay for PGOOD in 0.8 1 1.2 ms
Delay for PGOOD out, with 100 mV over drive 330 ns
tPGSSDLY PGOOD start-up delay CVREF = 0.1 μF, S5 rising to PGOOD rising 2.5 ms
PROTECTIONS
ITRIP TRIP source current TA = 25°C, VTRIP = 0.4 V 9 10 11 μA
TCITRIP TRIP source current temperature coefficient(1) 4700 ppm/°C
VTRIP VTRIP voltage range 0.2 3 V
VOCL Current limit threshold VTRIP = 3.0 V 360 375 390 mV
VTRIP = 1.6 V 190 200 210
VTRIP = 0.2 V 20 25 30
VOCLN Negative current limit threshold VTRIP = 3.0 V –390 –375 –360 mV
VTRIP = 1.6 V –210 –200 –190
VTRIP = 0.2 V –30 –25 –20
VZC Zero cross detection offset 0 mV
VUVLO V5IN UVLO threshold voltage Wake-up 4.2 4.4 4.5 V
Shutdown 3.7 3.9 4.1
VOVP VDDQ OVP threshold voltage OVP detect voltage 118% 120% 122%
tOVPDLY VDDQ OVP propagation delay With 100 mV over drive 430 ns
VUVP VDDQ UVP threshold voltage UVP detect voltage 66% 68% 70%
tUVPDLY VDDQ UVP delay 1 ms
tUVPENDLY VDDQ UVP enable delay 1.2 ms
VOOB OOB Threshold voltage 108%
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold(1) Shutdown temperature 140 °C
Hysteresis 10
(1) Ensured by design. Not production tested.