SLVSAE4A July   2010  – August 2014 TPS53128

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
      1. 7.2.1 16
      2. 7.2.2 17
    3. 7.3 Feature Description
      1. 7.3.1  PWM Operation
      2. 7.3.2  Light-Load Condition
      3. 7.3.3  Drivers
      4. 7.3.4  PWM Frequency And Adaptive On-Time Control
      5. 7.3.5  5-Volt Regulator
      6. 7.3.6  Soft Start
      7. 7.3.7  Pre-Bias Support
      8. 7.3.8  Output Discharge Control
      9. 7.3.9  Over Current Limit
      10. 7.3.10 Over/Under Voltage Protection
      11. 7.3.11 UVLO Protection
      12. 7.3.12 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
VALUE UNIT
VI Input voltage VIN, EN1, EN2 –0.3 to 26 V
VBST1, VBST2 –0.3 to 32
VBST1 - SW1, VBST2 - SW2 –0.3 to 6
V5FILT, VFB1, VFB2, TRIP1, TRIP2,
VO1, VO2		 –0.3 to 6
SW1, SW2 –2 to 26
VO Output voltage DRVH1, DRVH2 –1 to 32 V
DRVH1 - SW1, DRVH2 - SW2 –0.3 to 6
DRVL1, DRVL2, VREG5, SS1, SS2 –0.3 to 6
PGND1, PGND2 –0.3 to 0.3
TA Operating ambient temperature –40 to 85 °C
TJ Junction temperature –40 to 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range -55 150 °C
V(ESD) Electrostatic discharge Human body model (HBM), per AN/ESDA/JEDEC JS-001, all pins(1) –2000 2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) –500 500 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Supply input voltage VIN 4.5 24 V
V5FILT 4.5 5.5
VI Input voltage VBST1, VBST2 –0.1 30 V
VBST1 - SW1, VBST2 - SW2 –0.1 5.5
VFB1, VFB2, VO1, VO2 –0.1 5.5
TRIP1, TRIP2 –0.1 0.3
EN1, EN2 –0.1 24
SW1, SW2 –1.8 24
VO Output voltage DRVH1, DRVH2 –0.1 30 V
VBST1 - SW1, VBST2 - SW2 –0.1 5.5
DRVL1, DRVL2, VREG5, SS1, SS2 –0.1 5.5
PGND1, PGND2 –0.1 0.1
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS53128 UNIT
RGE PW
24 PIN 24PIN
RθJA Junction-to-ambient thermal resistance 35.4 88.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 39.1 26.5
RθJB Junction-to-board thermal resistance 13.6 43.5
ψJT Junction-to-top characterization parameter 0.5 1.1
ψJB Junction-to-board characterization parameter 13.6 43
RθJC(bot) Junction-to-case (bottom) thermal resistance 3.8 N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IIN VIN supply current VIN current, TA = 25°C, VREG5 tied to V5FILT, EN1 = EN2 = 5 V,
VFB1 = VFB2 = 0.8 V,
SW1 = SW2 = 0.5 V		 450 800 μA
IVINSDN VIN shutdown current VIN current, TA = 25°C,
no load , EN1 = EN2 = 0 V,
VREG5 = ON		 30 60 μA
VFB VOLTAGE AND DISCHARGE RESISTANCE
VBG Bandgap initial regulation accuracy TA = 25°C –1 1 %
VVFBTHx VFBx threshold voltage TA = 25°C, SWinj = OFF 755 765 775 mV
TA = 0°C to 70°C,
SWinj = OFF(1) 		753.5 776.5
TA = -40°C to 85°C,
SWinj = OFF (1) 		752 778
IVFB VFB input current VFBx = 0.8 V, TA = 25°C –100 –10 100 nA
RDischg VO discharge resistance ENx = 0 V, VOx = 0.5 V, TA = 25°C 40 80 Ω
VREG5 OUTPUT
VVREG5 VREG5 output voltage TA = 25°C, 5.5 V < VIN < 24 V,
0 < IVREG5 < 10 mA		 4.6 5.0 5.2 V
VLN5 Line regulation 5.5 V < VIN < 24 V, IVREG5 = 10 mA 20 mV
VLD5 Load regulation 1 mA < IVREG5 < 10 mA 40 mV
IVREG5 Output current VIN = 5.5 V, VREG5 = 4.0 V,
TA = 25°C		 170 mA
OUTPUT: N-CHANNEL MOSFET GATE DRIVERS
RDRVH DRVH resistance Source, IDRVHx = –100 mA 5.5 11 Ω
Sink, IDRVHx = 100 mA 2.5 5
RDRVL DRVL resistance Source, IDRVLx = –100 mA 4 12 Ω
Sink, IDRVLx = 100 mA 2 4
TD Dead time DRVHx-low to DRVLx-on 20 50 80 ns
DRVLx-low to DRVHx-on 20 40 80
INTERNAL BOOST DIODE
VFBST Forward voltage VVREG5-VBSTx, IF = 10 mA, TA = 25°C 0.7 0.8 0.9 V
IVBSTLK VBST leakage current VBSTx = 29 V, SWx = 24 V,
TA = 25°C		 0.1 1 μA
ON-TIME TIMER CONTROL
TON1L CH1 on time SW1 = 12 V, VO1 = 1.8 V 490 ns
TON2L CH2 on time SW2 = 12 V, VO2 = 1.8 V 390 ns
TOFF1L CH1 min off time SW1 = 0.7 V, TA = 25°C,
VFB1 = 0.7 V		 285 ns
TOFF2L CH2 min off time SW2 = 0.7 V, TA = 25°C,
VFB2 = 0.7 V 		285 ns
SOFT START
ISSC SS1/SS2 charge current VSS1/VSS2 = 0 V, TA = 25°C –2.5 –2 –1.5 μA
TCISSC ISSC temperature coefficient On the basis of 25°C(1) –4 3 nA/°C
ISSD SS1/SS2 discharge current VSS1/VSS2 = 0.5 V 100 150 μA
UVLO
VUV5VFILT V5FILT UVLO threshold Wake up 3.7 4.0 4.3 V
Hysteresis 0.2 0.3 0.4
LOGIC THRESHOLD
VENH ENx high-level input voltage EN 1/2 2.0 V
VENL ENx low-level input voltage EN 1/2 0.3 V
CURRENT SENSE
ITRIP TRIP source current VTRIPx = 0.1 V, TA = 25°C 8.5 10 11.5 μA
TCITRIP ITRIP temperature coefficient On the basis of 25°C 4000 ppm/°C
VOCLoff OCP compensation offset (VTRIPx-GND-VPGNDx-SWx) voltage,
VTRIPx-GND = 60 mV, TA = 25°C		 –15 0 15 mV
(VTRIPx-GND-VPGNDx-SWx) voltage,
VTRIPx-GND = 60 mV		 –20 20
VRtrip Current limit threshold setting range VTRIPx-GND voltage 30 300 mV
OUTPUT UNDERVOLTAGE AND OVERVOLTAGE PROTECTION
VOVP Output OVP trip threshold OVP detect 110 115 120 %
TOVPDEL Output OVP prop delay 1.5 μs
VUVP Output UVP trip threshold UVP detect 65 70 75 %
Hysteresis (recover < 20 μs) 10
TUVPDEL Output UVP delay 17 30 40 μs
TUVPEN Output UVP enable delay UVP enable delay / soft-start time x1.4 x1.7 x2.0 ms
THERMAL SHUTDOWN
TSDN Thermal shutdown threshold Shutdown temperature (1) 150 °C
Hysteresis (1) 20
(1) Not production tested - ensured by design.

6.6 Typical Characteristics

TPS53128 vin_is1_lvsae4.gif
Figure 1. VIN Supply Current
vs
Junction Temperature
TPS53128 itrip_lvs947.gif
Figure 3. Trip Source Current
vs
Junction Temperature
TPS53128 vregvvi_lvs947.gif
Figure 5. VREG5 Voltage
vs
Input Voltage
TPS53128 vfb2_vin_lvsae4.gif
Figure 7. VFB2 Voltage
vs
Input Voltage
TPS53128 vfb2_temp_lvsae4.gif
Figure 9. VFB2 Voltage
vs
Junction Temperature
TPS53128 vin_ishtdn_lvs947.gif
VREG5 = ON
Figure 2. VIN Shutdown Current
vs
Junction Temperature
TPS53128 vregvtemp_lvsae4.gif
Figure 4. VREG5 Voltage
vs
Junction Temperature
TPS53128 vfb1_vin_lvsae4.gif
Figure 6. VFB1 Voltage
vs
Input Voltage
TPS53128 vfb1_temp1_lvsae4.gif
Figure 8. VFB1 Voltage
vs
Junction Temperature