JAJS448D March   2010  – October 2018 TPS54260

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と負荷電流との関係
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Slope Compensation Output Current
      3. 8.3.3  Pulse-Skip Eco-Mode
      4. 8.3.4  Low-Dropout Operation and Bootstrap Voltage (BOOT)
      5. 8.3.5  Error Amplifier
      6. 8.3.6  Voltage Reference
      7. 8.3.7  Adjusting the Output Voltage
      8. 8.3.8  Enable and Adjusting Undervoltage Lockout
      9. 8.3.9  Slow-Start / Tracking Pin (SS/TR)
      10. 8.3.10 Overload Recovery Circuit
      11. 8.3.11 Sequencing
      12. 8.3.12 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
      13. 8.3.13 Overcurrent Protection and Frequency Shift
      14. 8.3.14 Selecting the Switching Frequency
      15. 8.3.15 How to Interface to RT/CLK Pin
      16. 8.3.16 Powergood (PWRGD Pin)
      17. 8.3.17 Overvoltage Transient Protection
      18. 8.3.18 Thermal Shutdown
      19. 8.3.19 Small Signal Model for Loop Response
      20. 8.3.20 Simple Small Signal Model for Peak Current Mode Control
      21. 8.3.21 Small Signal Model for Frequency Compensation
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation Near Minimum Input Voltage
      2. 8.4.2 Operation With Enable Control
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 3.3-V Output Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 9.2.1.2.2  Selecting the Switching Frequency
          3. 9.2.1.2.3  Output Inductor Selection (LO)
          4. 9.2.1.2.4  Output Capacitor
          5. 9.2.1.2.5  Catch Diode
          6. 9.2.1.2.6  Input Capacitor
          7. 9.2.1.2.7  Slow-Start Capacitor
          8. 9.2.1.2.8  Bootstrap Capacitor Selection
          9. 9.2.1.2.9  Undervoltage Lock Out Set Point
          10. 9.2.1.2.10 Output Voltage and Feedback Resistors Selection
          11. 9.2.1.2.11 Compensation
          12. 9.2.1.2.12 Discontinuous Mode and Eco-Mode Boundary
          13. 9.2.1.2.13 Power Dissipation Estimate
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Inverting Power Supply
      3. 9.2.3 Split-Rail Power Supply
      4. 9.2.4 12-V to 3.8-V GSM Power Supply
      5. 9.2.5 24-V to 4.2-V GSM Power Supply
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 12.1.2 開発サポート
        1. 12.1.2.1 WEBENCH®ツールによるカスタム設計
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.3 Pulse-Skip Eco-Mode

The TPS54260 operates in a pulse-skip Eco-Mode at light-load currents to improve efficiency by reducing switching and gate drive losses. The TPS54260 is designed so that if the output voltage is within regulation and the peak switch current at the end of any switching cycle is below the pulse-skipping current threshold, the device enters Eco-Mode. This current threshold is the current level corresponding to a nominal COMP voltage or 500mV.

When in Eco-Mode, the COMP pin voltage is clamped at 500 mV and the high-side MOSFET is inhibited. Further decreases in load current or in output voltage can not drive the COMP pin below this clamp voltage level.

Since the device is not switching, the output voltage begins to decay. As the voltage control loop compensates for the falling output voltage, the COMP pin voltage begins to rise. At this time, the high-side MOSFET is enabled and a switching pulse initiates on the next switching cycle. The peak current is set by the COMP pin voltage. The output voltage re-charges the regulated value, then the peak switch current starts to decrease, and eventually falls below the Eco-Mode threshold at which time the device again enters Eco-Mode.

For Eco-Mode operation, the TPS54260 senses peak current, not average or load current, so the load current where the device enters Eco-Mode is dependent on the output inductor value. For example, the circuit in Figure 50 enters Eco-Mode at about 5 mA of output current. When the load current is low and the output voltage is within regulation, the device enters a sleep mode and draws only 138-μA input quiescent current. The internal PLL remains operating when in sleep mode. When operating at light-load currents in the pulse-skip mode, the switching transitions occur synchronously with the external clock signal.