JAJSII5A January   2020  – March 2020 TPS59603-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 UVLO Protection
      2. 7.3.2 PWM Pin
      3. 7.3.3 SKIP Pin
        1. 7.3.3.1 Zero Crossing (ZX) Operation
      4. 7.3.4 Adaptive Dead-Time Control and Shoot-Through Protection
      5. 7.3.5 Integrated Boost-Switch
    4. 7.4 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Recommendation
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 開発サポート
    2. 10.2 ドキュメントのサポート
      1. 10.2.1 関連資料
    3. 10.3 コミュニティ・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 Glossary
  11. 11メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

These specifications apply for –40°C ≤ TJ ≤ 125°C, and VVDD = 5 V unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD INPUT SUPPLY
ICC Supply current (operating) VSKIP = VVDD or VSKIP = 0 V,
PWM = High		 160 600 µA
VSKIP = VVDD or VSKIP = 0 V,
PWM = Low		 250
VSKIP = VVDD or VSKIP = 0 V,
PWM = Float		 130
VSKIP = Float 8
VDD UNDERVOLTAGE LOCKOUT (UVLO)
VUVLO UVLO threshold Rising threshold 4.19 V
Falling threshold 3.65
VUVHYS UVLO hysteresis 0.2 V
PWM AND SKIP I/O SPECIFICATIONS
RI Input impedance Pullup to VDD 1.7 MΩ
Pulldown (to GND) 800 kΩ
VIL Low-level input voltage 0.6 V
VIH High-level input voltage 2.70 V
VIHH Hysteresis 0.2 V
VTS Tri-state voltage 1.3 2.0 V
tTHOLD(off1) Tri-state activation time (falling) PWM 60 ns
tTHOLD(off2) Tri-state activation time (rising) PWM 60 ns
tTSKF Tri-state activation time (falling) SKIP 1 µs
tTSKR Tri-state activation time (rising) SKIP 1 µs
t3RD(PWM) Tri-state exit time PWM 100 ns
t3RD(SKIP) Tri-state exit time SKIP 50 µs
HIGH-SIDE GATE DRIVER (DRVH)
tR(DRVH) Rise time DRVH rising, CDRVH = 3.3 nF; 20% to 80% 30 ns
tRPD(DRVH) Rise time propogation delay CDRVH = 3.3 nF 40 ns
RSRC Source resistance Source resistance,
(VBST– VSW) = 5 V,
high state, (VBST – VDRVH) = 0.1 V		 2 4 Ω
tF(DRVH) Fall time DRVH falling, CDRVH = 3.3 nF 8 ns
tFPD(DRVH) Fall-time propagation delay CDRVH = 3.3 nF 25 ns
RSNK Sink resistance Sink resistance,
(VBST – VSW) forced to 5 V,
low state (VDRVH – VSW) = 0.1 V		 0.5 1.6 Ω
RDRVH DRVH to SW resistance(1) 100 kΩ
LOW-SIDE GATE DRIVER (DRVL)
tR(DRVL) Rise time DRVL rising, CDRVL = 3.3 nF; 20% to 80% 15 ns
tRPD(DRVL) Rise time propagation delay CDRVL = 3.3 nF 35 ns
RSRC Source resistance Source resistance, (VVDD–GND) = 5 V,
high state, (VVDD – VDRVL) = 0.1 V		 1.5 3 Ω
tF(DRVL) Fall time DRVL falling, CDRVL = 3.3 nF 10 ns
tFPD(DRVL) Fall-time propagation delay CDRVL= 3.3 nF 15 ns
RSNK Sink resistance Sink resistance, (VVDD– GND) = 5 V,
low state, (VDRVL – GND) = 0.1 V		 0.4 1.6 Ω
RDRVL DRVL to GND resistance(1) 100 kΩ
GATE DRIVER DEAD-TIME
tR(DT) Rising edge 0 20 40 ns
tF(DT) Falling edge 0 10 25 ns
ZERO CROSSING COMPARATOR
VZX Zero crossing offset SW voltage rising –2.25 0 2.00 mV
BOOTSTRAP SWITCH
VFBST Forward voltage IF = 10 mA 120 240 mV
IRLEAK Reverse leakage (VBST – VVDD) = 25 V 2 µA
RDS(on) On-resistance 12 24 Ω
(1) Specified by design. Not production tested.