JAJSSX0B January   2022  – January 2024 TPS61376

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 VCC Power Supply
      2. 6.3.2 Enable and Programmable UVLO
      3. 6.3.3 Soft Start and Inrush Current Control During Start-Up
      4. 6.3.4 Switching Frequency
      5. 6.3.5 Adjustable input average Current Limit
      6. 6.3.6 Shut Down and Load Disconnect
      7. 6.3.7 Overvoltage Protection
      8. 6.3.8 Output Short Protection
      9. 6.3.9 Thermal Shutdown
    4. 6.4 Device Functional Modes
      1. 6.4.1 PWM Mode
      2. 6.4.2 Auto PFM Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Setting Output Voltage
        2. 7.2.2.2 Inductor Selection
        3. 7.2.2.3 Bootstrap Capacitor Selection
        4. 7.2.2.4 Input Capacitor Selection
        5. 7.2.2.5 Output Capacitor Selection
        6. 7.2.2.6 Diode Selection
        7. 7.2.2.7 Loop Stability
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2.2.5 Output Capacitor Selection

The output capacitor is mainly selected to meet the requirements at load transient or steady state. The loop is compensated for the output capacitor selected. The output ripple voltage is related to the equivalent series resistance (ESR) of the capacitor and its capacitance. Assuming a capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by Equation 9:

Equation 9. GUID-74E54D3F-F3F4-48A1-991E-562309201F9C-low.gif

where

  • COUT is the output capacitor
  • IOUT is the output current
  • VOUT is the output voltage
  • VIN is the input voltage
  • ΔV is the output voltage ripple required
  • ƒSW is the switching frequency

The additional output ripple component caused by ESR is calculated by Equation 10:

Equation 10. ∆VESR=ILpeak× RESR

where

  • ΔVESR is the output voltage ripple caused by ESR
  • RESR is the resistor in series with the output capacitor

For the ceramic capacitor, the ESR ripple can be neglected. However, for the tantalum or electrolytic capacitors, it must be considered if used.

The minimum ceramic output capacitance needed to meet a load transient requirement can be estimated using Equation 11:

Equation 11. GUID-0B19C42C-79F0-4F6E-9AEF-F3F0133C214E-low.gif

where

  • ΔISTEP is the transient load current step
  • ΔVTRAN is the allowed voltage dip for the load current step
  • ƒBW is the control loop bandwidth (that is, the frequency where the control loop gain crosses zero)

Take care when evaluating the derating of a ceramic capacitor under the DC bias. Ceramic capacitors can derate by as much as 70% of the capacitance at the respective rated voltage. Therefore, enough margins on the voltage rating must be considered to ensure adequate capacitance at the required output voltage.