JAJSI40C July   2019  – February 2020 TPS63810 , TPS63811

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
      2.      効率と出力電流との関係
  4. 4 改訂履歴
  5. 5 デバイス比較表
  6. 6 Pin Configuration and Functions
    1.     BGA Package (YFF) Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Control Scheme
        1. 8.3.1.1 Buck Operation
        2. 8.3.1.2 Boost Operation
        3. 8.3.1.3 Buck-Boost Operation
      2. 8.3.2  Control Scheme
      3. 8.3.3  Power-Save Mode Operation (PSM)
      4. 8.3.4  Forced-PWM Operation (FPWM)
      5. 8.3.5  Ramp-PWM Operation (RPWM)
      6. 8.3.6  Device Enable (EN)
      7. 8.3.7  Undervoltage Lockout (UVLO)
      8. 8.3.8  Soft Start
      9. 8.3.9  Output Voltage Control
        1. 8.3.9.1 Dynamic Voltage Scaling
      10. 8.3.10 Protection Functions
        1. 8.3.10.1 Input Voltage Protection (IVP)
        2. 8.3.10.2 Current Limit Mode and Overcurrent Protection
        3. 8.3.10.3 Thermal Shutdown
      11. 8.3.11 Power Good
      12. 8.3.12 Load Disconnect
      13. 8.3.13 Output Discharge
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
      2. 8.5.2 Standard-, Fast-, and Fast-Mode Plus Protocol
      3. 8.5.3 I2C Update Sequence
    6. 8.6 Register Map
      1. 8.6.1 Register Description
        1. 8.6.1.1 Register Map
        2. 8.6.1.2 Register CONTROL (Slave address: 0b1110101; Register address: 0x01; Default: 0x00 or 0x20)
          1. Table 3. Register CONTROL Field Descriptions
        3. 8.6.1.3 Register STATUS (Slave address: 0b1110101; Register address: 0x02; Default: 0x00)
          1. Table 4. Register STATUS Field Descriptions
        4. 8.6.1.4 Register DEVID (Slave address: 0b1110101; Register address: 0x03; Default: 0x04)
          1. Table 5. Register DEVID Field Descriptions
        5. 8.6.1.5 Register VOUT1 (Slave address: 0b1110101; Register address: 0x04; Default: 0x3C)
          1. Table 6. Register VOUT1 Field Descriptions
        6. 8.6.1.6 Register VOUT2 (Slave address: 0b1110101; Register address: 0x05; Default: 0x42)
          1. Table 7. Register VOUT2 Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 1.8-V to 5.2-V Output Smartphone Power Supply
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Input Capacitor Selection
          2. 9.2.1.2.2 Inductor Selection
          3. 9.2.1.2.3 Output Capacitor Selection
          4. 9.2.1.2.4 I2C Pullup Resistor Selection
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 サポート・リソース
    6. 12.6 商標
    7. 12.7 用語集
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7 Switching Characteristics

Over operating junction temperature range and recommended input voltage range (unless otherwise noted). Typical values are at VI = 3.6 V, VO = 3.3 V, and TJ = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(EN) Delay between a rising edge on the
EN pin and the start of the output
voltage ramp		 TJ = 25°C, VI = 3.6 V 229 440 µs
td(PG) Power-good delay VO falling 50 µs
SR Slew rate of internal ramp during dynamic voltage scaling SLEW = 00b, forced-PWM operation ±1 V/ms
SLEW = 01b, forced-PWM operation ±2.5
SLEW = 10b, forced-PWM operation ±5
SLEW = 11b, forced-PWM operation ±10
fSW  Inductor Switching Frequency, Boost Mode VI = 2.3 V, VO = 3.3 V, no Load, PWM operation 2.6 MHz
Inductor Switching Frequency, Buck-Boost Mode VI = 3.3 V, VO = 3.3 V, no Load, PWM operation 1.6 MHz
Inductor Switching Frequency, Buck Mode VI = 4.3 V, VO = 3.3 V, no Load, PWM operation 2.0 MHz
td(VSEL) Delay between rising edge of VSEL and start of DVS ramp Measured from rising edge of VSEL to start of ramp. 5 µs