SLVSB04A July   2011  – August 2015 TPS65186

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: Data Transmission
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Wake-Up and Power-Up Sequencing
      2. 8.3.2  Dependencies Between Rails
      3. 8.3.3  Soft Start
      4. 8.3.4  VPOS/VNEG Supply Tracking
      5. 8.3.5  V3P3 Power Switch
      6. 8.3.6  VCOM Adjustment
        1. 8.3.6.1 Kick-Back Voltage Measurement
        2. 8.3.6.2 Storing the VCOM Power-Up Default Value in Memory
      7. 8.3.7  Fault Handling and Recovery
      8. 8.3.8  Power Good Pin
      9. 8.3.9  Interrupt Pin
      10. 8.3.10 Panel Temperature Monitoring
        1. 8.3.10.1 NTC Bias Circuit
        2. 8.3.10.2 Hot, Cold, and Temperature-Change Interrupts
        3. 8.3.10.3 Typical Application of the Temperature Monitor
    4. 8.4 Device Functional Modes
      1. 8.4.1 SLEEP
      2. 8.4.2 STANDBY
      3. 8.4.3 ACTIVE
      4. 8.4.4 Mode Transitions
        1. 8.4.4.1 SLEEP → ACTIVE
        2. 8.4.4.2 SLEEP → STANDBY
        3. 8.4.4.3 STANDBY → ACTIVE
        4. 8.4.4.4 ACTIVE → STANDBY
        5. 8.4.4.5 STANDBY → SLEEP
        6. 8.4.4.6 ACTIVE → SLEEP
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
    6. 8.6 Register Maps
      1. 8.6.1  Thermistor Readout (TMST_VALUE)
      2. 8.6.2  Enable (ENABLE)
      3. 8.6.3  Voltage Adjustment Register (VADJ)
      4. 8.6.4  VCOM 1 (VCOM1)
      5. 8.6.5  VCOM 2 (VCOM2)
      6. 8.6.6  Interrupt Enable 1 (INT_EN1)
      7. 8.6.7  Interrupt Enable 2 (INT_EN2)
      8. 8.6.8  Interrupt 1 (INT1)
      9. 8.6.9  Interrupt 2 (INT2)
      10. 8.6.10 Power Up Sequence Register 0 (UPSEQ0)
      11. 8.6.11 Power Up Sequence Register 1 (UPSEQ1)
      12. 8.6.12 Power Down Sequence Register 0 (DWNSEQ0)
      13. 8.6.13 Power Down Sequence Register 1 (DWNSEQ1)
      14. 8.6.14 Thermistor Register 1 (TMST1)
      15. 8.6.15 Thermistor Register 2 (TMST2)
      16. 8.6.16 Power Good Status (PG)
      17. 8.6.17 Revision and Version Control (REVID)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Power Supply Recommendations

The device is designed to operate with an input voltage supply range from 3 V to 6 V. This input supply can be from an externally regulated supply. If the input supply is located more than a few inches from the TPS65186, additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic capacitor with a value of 10 µF is a typical choice.