The primary communication between the device and the system MCU is through a SPI bus. The SPI bus provides full-duplex communication in a master-slave configuration. The system MCU is always a SPI master device that sends command requests on the SDI pin and receives device responses on the SDO pin. The TPS65313-Q1 device is always a SPI slave device that receives command requests and sends responses (status and measured values) to the external MCU over the SDO line.

The features of the SPI are listed as follows:

• A four-pin interface that includes the following pins:
  • NCS, which is the SPI chip select (active low).
  • SCK, which is the SPI clock.
  • SDI, which is the SPI slave-in and master-out (SIMO) pin.
  • SDO, which is the SPI slave-out and master-in (SOMI) tri-state output.
• A frame size of 24 bits or 16 bits that includes the following:
  • 24 bits
    • 8 bits for commands
    • 8 bits for data
    • 8 bits for CRC when SPI CRC protection is enabled
  • 16 bits
    • 8 bits for commands
    • 8 bits for data
• Data rate of up to 8 Mbps
• The commands and data shift with the most significant bit (MSB) first and the least significant bit (LSB) last.
• On the falling edge of the SCK pin, the SPI samples the SDI line.
• On the rising edge of the SCK pin, the SPI shifts out the data on the SDO pin.

The SPI communication starts with the falling edge of the NCS pin, and ends with the rising edge of the NCS pin. A logic-high level on the NCS pin of the device keeps the SPI of the device in the RESET state and the SDO pin in the high-impedance state (tri-state). The SPI is disabled when the device is in the OFF, INIT, or RESET state (the device returns all 0 s to any SPI command request).

When the TPS65313-Q1 device releases the NRES pin output buffer driver in the DIAGNOSTIC, ACTIVE, or SAFE state, the SPI is accessible regardless of the state of the NRES pin. The NRES_ERR status bit in the SAFETY_ERR_STAT register is set to 1b in case a mismatch between the input of NRES output buffer driver and the output of the NRES input buffer driver is detected.

The size configuration of the SPI frame occurs only in the DIAGNOSTIC state. The default SPI frame is 16-bits (without the CRC-protection field). The SPI frame-size configuration bit is protected by the device-configuration CRC (DEV_CFG_CRC) protection mechanism.

The SPI does not support back-to-back (burst) SPI-frame operation. Instead, after each SPI command (either a SPI read or SPI write access), the NCS pin must change from low to high before the next SPI transfer can start. The minimum time, t_hl(cs), between two SPI commands during which the NCS pin must stay high is 788 ns.