JAJSIR5C October 2019 – October 2023 TPS65313-Q1
PRODUCTION DATA
The TPS65313-Q1 device includes one clock monitor in the analog domain (ACLKMNT) and six clock monitors in the digital domain (DCLKMNT) as shown in Table 11-2. The stable system clock (SYSCLK) for the digital core with reasonable frequency accuracy is a prerequisite to device power-up. The analog clock monitor (ACLKMNT) monitors the SYSCLK frequency before the download of trim data from the EEPROM. During a device power-up event, if the SYSCLK does not start switching with defined accuracy limits within the tSTART_UP_TO time, the device goes back to the OFF state and latches the failure conditions (SYSCLK error and power-up time-out) in the Analog_Latch.
The EEPROM trim content is downloaded when the digital core is out of the NPOR condition. If the EEPROM content is downloaded without error, the DCLKMNT monitors are enabled.
DCLKMNT monitors monitor the health of the clocks along the clock tree. The clock tree generates three switching clocks for the BUCK1 regulator, BUCK2 regulator, and BOOST converter. Table 11-2 summarizes the DCLKMNT monitors. For more information on device behavior when each DCLKMNT monitor detects a clock error condition, see Section 11.7.
| MONITOR | MONITORED CLOCK | REFERENCE CLOCK | STATUS BIT IN SAFETY_CLK_STAT REGISTER | STATUS BIT IN SAFETY_CLK_WARN_STAT REGISTER |
|---|---|---|---|---|
| DIG_CLK_MON1 | SYNC_IN clock | SYSCLK | Bit 2, SYNC_CLK_ERR | Bit 2, SYNC_CLK_WARN |
| DIG_CLK_MON2(3) | SYSCLK | MODCLK or PLL clock(1) | Bit 0, DIG_SYSCLK_ERR | — |
| DIG_CLK_MON3 | BUCK1_CLK(2) | SYSCLK | Bit 3, BUCK1_FSW_CLK_ERR | Bit 3, BUCK1_FSW_CLK_WARN |
| DIG_CLK_MON4 | BUCK2_CLK(2) | SYSCLK | Bit 4, BUCK2_FSW_CLK_ERR | Bit 4, BUCK2_FSW_CLK_WARN |
| DIG_CLK_MON5 | BOOST_CLK(2) | SYSCLK | Bit 6, BOOST_FSW_CLK_ERR | Bit 6, BOOST_FSW_CLK_WARN |
| DIG_CLK_MON6 | PLL VCO clock, or MODCLK | SYSCLK | Bit 1, SMPS_SRC_CLK_ERR | Bit 1, SMPS_SRC_CLK_WARN |
The clock monitors detect if the monitored clock is either too fast or too slow.
As defined in the SAFETY_CLK_WARN_STAT register, the DIG_CLK_MONs monitors provide an early-warning flag before a clock error is detected. Depending on the SYSCLK frequency variation (8 MHz ± 5 %), the switched-mode regulators can operate for some time with a clock in a range where electrical parameters and performance cannot be ensured before a clock error is detected. This detection interval can be up to 143 cycles of an 8-MHz SYSCLK clock, or up to 18 µs.
All the DCLKMNT monitors are enabled by default except the SYNC_IN clock monitor (DIG_CLK_MON1). These clock monitors do not have considerable impact on the device functional safety coverage and critical regulator faults are covered with other safety mechanisms in the device. The system MCU can disable DCLKMNT clock monitors through the CLK_MON_CTRL register, if these clock monitors are generating false clock monitoring warnings or errors due to system level noise issues. The ACLKMNT monitor cannot be disabled. When enabled, the DCLKMNT monitors continuously monitor clocks within the defined limits for fast and slow clock. All clock monitors are checked by the built-in-self-test diagnostics.