JAJSIR5C October   2019  – October 2023 TPS65313-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 デバイスの機能ブロック図
  6. 5 Revision History
  7. 6 概要 (続き)
  8. 7 Device Option Table
  9. 8 Pin Configuration and Functions
  10. 9 Specifications
    1. 9.1  Absolute Maximum Ratings
    2. 9.2  ESD Ratings
    3. 9.3  Recommended Operating Conditions
    4. 9.4  Thermal Information
    5. 9.5  Power-On-Reset, Current Consumption, and State Timeout Characteristics
    6. 9.6  PLL/Oscillator and SYNC_IN Pin Characteristics
    7. 9.7  Wide-VIN Synchronous Buck Regulator (Wide-VIN BUCK) Characteristics
    8. 9.8  Low-Voltage Synchronous Buck Regulator (LV BUCK) Characteristics
    9. 9.9  Synchronous Boost Converter (BOOST) Characteristics
    10. 9.10 Internal Voltage Regulator (VREG) Characteristics
    11. 9.11 Voltage Monitors for Regulators Characteristics
    12. 9.12 External General Purpose Voltage Monitor Characteristics
    13. 9.13 VIN and VIN_SAFE Under-Voltage and Over-Voltage Warning Characteristics
    14. 9.14 WAKE Input Characteristics
    15. 9.15 NRES (nRESET) Output Characteristics
    16. 9.16 ENDRV/nIRQ Output Characteristics
    17. 9.17 Analog DIAG_OUT
    18. 9.18 Digital INPUT/OUTPUT IOs (SPI Interface IOs, DIAG_OUT/SYNC_OUT, MCU_ERROR)
    19. 9.19 BUCK1, BUCK2, BOOST Thermal Shutdown / Over Temperature Protection Characteristics
    20. 9.20 PGNDx Loss Detection Characteristics
    21. 9.21 SPI Timing Requirements
    22. 9.22 SPI Characteristics
    23. 9.23 Typical Characteristics
  11. 10Parameter Measurement Information
  12. 11Detailed Description
    1. 11.1  Overview
    2. 11.2  Functional Block Diagram
    3. 11.3  Wide-VIN Buck Regulator (BUCK1)
      1. 11.3.1 Fixed-Frequency Voltage-Mode Step-Down Regulator
      2. 11.3.2 Operation
      3. 11.3.3 Voltage Monitoring (Monitoring and Protection)
      4. 11.3.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.3.5 Thermal Warning and Shutdown Protection (Monitoring and Protection)
      6. 11.3.6 Overvoltage Protection (OVP) (Monitoring and Protection)
      7. 11.3.7 Extreme Overvoltage Protection (EOVP) (Monitoring and Protection)
    4. 11.4  Low-Voltage Buck Regulator (BUCK2)
      1. 11.4.1 Fixed-Frequency Peak-Current Mode Step-Down Regulator
      2. 11.4.2 Operation
      3. 11.4.3 Output Voltage Monitoring (Monitoring and Protection)
      4. 11.4.4 Overcurrent Protection (Monitoring and Protection)
      5. 11.4.5 Thermal Sensor Warning and Thermal Shutdown Protection (Monitoring and Protection)
      6. 11.4.6 Overvoltage Protection (OVP) (Monitoring and Protection)
    5. 11.5  Low-Voltage Boost Converter (BOOST)
      1. 11.5.1 Output Voltage Monitoring (Monitoring and Protection)
      2. 11.5.2 Overcurrent Protection (Monitoring and Protection)
      3. 11.5.3 Thermal Sensor Warning and Shutdown Protection (Monitoring and Protection)
      4. 11.5.4 Overvoltage Protection (OVP) (Monitoring and Protection)
    6. 11.6  VREG Regulator
    7. 11.7  BUCK1, BUCK2, and BOOST Switching Clocks and Synchronization (SYNC_IN) Clock
      1. 11.7.1 Internal fSW Clock Configuration (fSW Derived from an Internal Oscillator)
      2. 11.7.2 BUCK1 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      3. 11.7.3 BUCK2 Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      4. 11.7.4 BOOST Switching Clock-Monitor Error (Internal fSW Clock Configuration)
      5. 11.7.5 External fSW Clock Configuration (fSW Derived from SYNC_IN and PLL Clocks)
        1. 11.7.5.1 SYNC_IN, PLL, and VCO Clock Monitors
        2. 11.7.5.2 BUCK1 Switching Clock-Monitor Error (External fSW Clock Configuration)
        3. 11.7.5.3 BUCK2 Switching Clock-Monitor Error (External fSW Clock Configuration)
        4. 11.7.5.4 BOOST Switching Clock-Monitor Error (External fSW Clock Configuration)
    8. 11.8  BUCK1, BUCK2, and BOOST Switching-Clock Spread-Spectrum Modulation
    9. 11.9  Monitoring, Protection and Diagnostics Overview
      1. 11.9.1  Safety Functions and Diagnostic Overview
      2. 11.9.2  Supply Voltage Monitor (VMON)
      3. 11.9.3  Clock Monitors
      4. 11.9.4  Analog Built-In Self-Test
        1. 11.9.4.1 ABIST During Power-Up or Start-Up Event
        2. 11.9.4.2 ABIST in the RESET state
        3. 11.9.4.3 ABIST in the DIAGNOSTIC, ACTIVE, and SAFE State
        4. 11.9.4.4 ABIST Scheduler in the ACTIVE State
      5. 11.9.5  Logic Built-In Self-Test
      6. 11.9.6  Junction Temperature Monitors
      7. 11.9.7  Current Limit
      8. 11.9.8  Loss of Ground (GND)
      9. 11.9.9  Diagnostic Output Pin (DIAG_OUT)
        1. 11.9.9.1 Analog MUX Mode on DIAG_OUT
        2. 11.9.9.2 Digital MUX Mode on DIAG_OUT
          1. 11.9.9.2.1 MUX-Output Control Mode
          2. 11.9.9.2.2 Device Interconnect Mode
      10. 11.9.10 Watchdog
        1. 11.9.10.1 WD Question and Answer Configurations
        2. 11.9.10.2 WD Failure Counter and WD Status
        3. 11.9.10.3 WD SPI Event Definitions
        4. 11.9.10.4 WD Q&A Sequence Run
        5. 11.9.10.5 WD Question and Answer Value Generation
          1. 11.9.10.5.1 WD Initialization Events
      11. 11.9.11 MCU Error Signal Monitor
      12. 11.9.12 NRES Driver
      13. 11.9.13 ENDRV/nIRQ Driver
      14. 11.9.14 CRC Protection for the Device Configuration Registers
      15. 11.9.15 CRC Protection for the Device EEPROM Registers
    10. 11.10 General-Purpose External Supply Voltage Monitors
    11. 11.11 Analog Wake-up and Failure Latch
    12. 11.12 Power-Up and Power-Down Sequences
    13. 11.13 Device Fail-Safe State Controller (Monitoring and Protection)
      1. 11.13.1 OFF State
      2. 11.13.2 INIT State
      3. 11.13.3 RESET State (ON Transition From the INIT State)
      4. 11.13.4 RESET State (ON Transition From DIAGNOSTIC, ACTIVE, and SAFE State)
      5. 11.13.5 DIAGNOSTIC State
      6. 11.13.6 ACTIVE State
      7. 11.13.7 SAFE State
      8. 11.13.8 State Transition Priorities
    14. 11.14 Wakeup
    15. 11.15 Serial Peripheral Interface (SPI)
      1. 11.15.1 SPI Command Transfer Phase
      2. 11.15.2 SPI Data Transfer Phase
      3. 11.15.3 Device SPI Status Flag Response Byte
      4. 11.15.4 Device SPI Data Response
      5. 11.15.5 Device SPI Master CRC (MCRC) Input
      6. 11.15.6 Device SPI Slave CRC (SCRC) Output
      7. 11.15.7 SPI Frame Overview
    16. 11.16 Register Maps
      1. 11.16.1 Device SPI Mapped Registers
        1. 11.16.1.1 Memory Maps
          1. 11.16.1.1.1 SPI Registers
  13. 12Applications, Implementation, and Layout
    1. 12.1 Application Information
    2. 12.2 Typical Application
      1. 12.2.1 Design Requirements
      2. 12.2.2 Detailed Design Procedure
        1. 12.2.2.1  Selecting the BUCK1, BUCK2, and BOOST Output Voltages
        2. 12.2.2.2  Selecting the BUCK1, BUCK2, and BOOST Inductors
        3. 12.2.2.3  Selecting the BUCK1 and BUCK2 Output Capacitors
        4. 12.2.2.4  Selecting the BOOST Output Capacitors
        5. 12.2.2.5  Input Filter Capacitor Selection for BUCK1, BUCK2, and BOOST
        6. 12.2.2.6  Input Filter Capacitors on AVIN and VIN_SAFE Pins
        7. 12.2.2.7  Bootstrap Capacitor Selection
        8. 12.2.2.8  Internal Linear Regulator (VREG) Output Capacitor Selection
        9. 12.2.2.9  EXTSUP Pin
        10. 12.2.2.10 WAKE Input Pin
        11. 12.2.2.11 VIO Supply Pin
        12. 12.2.2.12 External General-Purpose Voltage Monitor Input Pins (EXT_VSENSE1 and EXT_VSENSE2)
        13. 12.2.2.13 SYNC_IN Pin
        14. 12.2.2.14 MCU_ERR Pin
        15. 12.2.2.15 NRES Pin
        16. 12.2.2.16 ENDRV/nIRQ Pin
        17. 12.2.2.17 DIAG_OUT Pin
        18. 12.2.2.18 SPI Pins (NCS,SCK, SDI, SDO)
        19. 12.2.2.19 PBKGx, AGND, DGND, and PGNDx Pins
        20. 12.2.2.20 Calculations for Power Dissipation and Junction Temperature
          1. 12.2.2.20.1 BUCK1 Output Current Calculation
          2. 12.2.2.20.2 Device Power Dissipation Estimation
          3. 12.2.2.20.3 Device Junction Temperature Estimation
            1. 12.2.2.20.3.1 Example for Device Junction Temperature Estimation
      3. 12.2.3 Application Curves
      4. 12.2.4 Layout
        1. 12.2.4.1 Layout Guidelines
        2. 12.2.4.2 Layout Example
        3. 12.2.4.3 Considerations for Board-Level Reliability (BLR)
    3. 12.3 Power Supply Coupling and Bulk Capacitors
  14. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 サポート・リソース
    4. 13.4 Trademarks
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

11.16.1 Device SPI Mapped Registers

The tables in this section lists the available SPI registers and includes an explanation of each bit function. For each SPI register, the bit names are given, with the default values, which are the values after internal logic reset and when the device is in the RESET state. These default values apply after each wake-up event when the device goes to the RESET state.

Table 11-22 lists the SPI commands. The name of a SPI read command starts with the RD_ prefix and the name of a SPI write command name starts with the WR_ prefix.

Table 11-22 SPI Command Space Table
Command No. Register No. Command Code Command Type WR SW Lock Protection Command Name
1 0xC1 Single SPI execution commands without associated memory-mapped register — SET_CTRL_LOCK with data 0x55 (to lock SPI WR access to listed control registers)
2 0xC2 — CLR_CTRL_LOCK with data 0xAA (to unlock SPI WR access to listed control registers)
3 0xF1 — SET_CTRL_BIST_LOCK with data 0x55 (to lock SPI WR access to listed ABIST and LBIST control registers)
4 0xF2 — CLR_CTRL_BIST_LOCK with data 0xAA (to unlock SPI WR access to listed ABIST and LBIST control registers)
5 0xC4 — SET_CFG_LOCK with data 0x55 (to lock SPI WR access to listed configuration registers)
6 0xC7 — CLR_CFG_LOCK with data 0xAA (to unlock SPI WR access to listed configuration registers)
7 0xDE — CLR_WAKE_LATCH with data 0x8E (to clear WAKE_L status bit)
8 0xF8 — MCU_RST_REQ with data 0x5A (to initiate the device transition to the RESET state)
9 0xF4 — CLR_AUTO_START_DIS with data 0x55 (to clear AUTO_START_DIS bit)
10 0xF7 — SET_AUTO_START_DIS with data 0xAA (to set AUTO_START_DIS bit)
11 1 0x01 — RD_DEV_REV
12 2 0x02 — RD_DEV_ID
13 3 0x07 SPI status register commands — RD_DEV_STAT1
14 4 0x08 — RD_DEV_STAT2
15 5 0xFB SPI configuration register commands (with WR SW lock state controlled by SET_CFG_LOCK and CLR_CFG_LOCK commands) YES WR_DEV_CFG1 (SPI WR update can occur only in the DIAGNOSTIC state)
16 0x0B — RD_DEV_CFG1
17 6 0xFD YES WR_DEV_CFG2 (SPI WR update can occur only in the DIAGNOSTIC state)
18 0x0D — RD_DEV_CFG2
19 7 0xFE YES WR_DEV_CFG3 (SPI WR update can occur only in the DIAGNOSTIC state)
20 0x0E — RD_DEV_CFG3
21 8 0xE1 YES WR_DEV_CFG4 (SPI WR update can occur only in the DIAGNOSTIC state)
22 0x11 — RD_DEV_CFG4
23 9 0xE2 YES WR_SAFETY_CFG1 (SPI WR update can occur only in the DIAGNOSTIC state)
24 0x12 — RD_SAFETY_CFG1
25 10 0xE4 YES WR_SAFETY_CFG2 (SPI WR update can occur only in the DIAGNOSTIC state)
26 0x14 — RD_SAFETY_CFG2
27 11 0xE7 YES WR_SAFETY_CFG3 (SPI WR update can occur only in the DIAGNOSTIC state)
28 0x17 — RD_SAFETY_CFG3
29 12 0xE8 YES WR_SAFETY_CFG4 (SPI WR update can occur only in the DIAGNOSTIC state)
30 0x18 — RD_SAFETY_CFG4
31 13 0xEB YES WR_SAFETY_CFG5 (SPI WR update can occur only in the DIAGNOSTIC state)
32 0x1B — RD_SAFETY_CFG5
33 14 0xED YES WR_SAFETY_CFG6 (SPI WR update can occur only in the DIAGNOSTIC state)
34 0x1D — RD_SAFETY_CFG6
37 16 0xD2 YES WR_SAFETY_CFG8 (SPI WR update can occur only in the DIAGNOSTIC state)
38 0x22 — RD_SAFETY_CFG8
39 17 0xD4 YES WR_EXT_VMON1_CFG (SPI WR update can occur only in the DIAGNOSTIC state)
40 0x24 — RD_EXT_VMON1_CFG
41 18 0xD7 YES WR_EXT_VMON2_CFG (SPI WR update can occur only in the DIAGNOSTIC state)
42 0x27 — RD_EXT_VMON2_CFG
43 19 0xD8 SPI control register commands (with WR SW lock state controlled by SET_CTRL_LOCK and CLR_CTRL_LOCK commands) YES WR_PWR_CTRL
44 0x28 — RD_PWR_CTRL
45 20 0xDD YES WR_CLK_MON_CTRL
46 0x2D — RD_CLK_MON_CTRL
47 21 0x2E SPI status register commands — RD_VMON_UV_STAT
48 22 0x31 — RD_VMON_OV_STAT
49 23 0x32 — RD_EXT_VMON_STAT
50 24 0x34 — RD_SAFETY_BUCK1_STAT1
51 25 0x37 — RD_SAFETY_BUCK1_STAT2
52 26 0x38 — RD_SAFETY_BUCK2_STAT1
53 27 0x3B — RD_SAFETY_BUCK2_STAT2
54 28 0x3D — RD_SAFETY_BOOST_STAT1
55 29 0x3E — RD_SAFETY_BOOST_STAT2
56 30 0x41 — RD_SAFETY_ERR_STAT1
57 31 0x42 — RD_SAFETY_CLK_STAT
58 32 0xCE — RD_SAFETY_CLK_WARN_STAT
59 33 0x44 — RD_SAFETY_ABIST_ERR_STAT1
60 34 0x47 — RD_SAFETY_ABIST_ERR_STAT2
61 35 0x48 — RD_SAFETY_ABIST_ERR_STAT3
62 36 0x4B — RD_SAFETY_ABIST_ERR_STAT4
63 37 0x4D — RD_SAFETY_ABIST_ERR_STAT5
64 38 0x4E — RD_SAFETY_ABIST_ERR_STAT6
65 39 0x51 — RD_SAFETY_LBIST_ERR_STAT
66 40 0x52 — RD_SAFETY_ERR_STAT2
67 0xA4 SPI status register commands (with WR SW lock state controlled by SET_CFG_LOCK and CLR_CFG_LOCK commands) YES WR_WD_FC (SPI WR update can occur only in the DIAGNOSTIC state and updates only the WD_FAIL_CNT[3:0] bits in the SAFETY_ERR_STAT2 register)
68 41 0x54 — RD_SAFETY_ERR_STAT3
69 0xA7 YES WR_MCU_ESM_FC (SPI WR update can occur only in the DIAGNOSTIC state and updates only the MCU_ESM_FC[3:0 bits in the SAFETY_ERR_STAT3 register)
70 42 0x57 — RD_SAFETY_ERR_STAT4
71 0xA8 YES WR_DEV_ERR_CNT (SPI WR update can occur only in the DIAGNOSTIC state and updates only the DEV_ERR_CNT[3:0 bits in the SAFETY_ERR_STAT4 register)
72 45 0x58 — RD_SPI_TRANSFER_STAT
73 46 0xAB SPI control register commands NO WR_SAFETY_ABIST_CTRL
74 0x5B — RD_SAFETY_ABIST_CTRL
75 47 0xAD NO WR_SAFETY_LBIST_CTRL
76 0x5D — RD_SAFETY_LBIST_CTRL
77 48 0xAE NO WR_SAFETY_CHECK_CTRL
78 0x5E — RD_SAFETY_CHECK_CTRL
79 49 0x91 SPI configuration register commands (with WR SW lock state controlled by SET_CFG_LOCK and CLR_CFG_LOCK commands) YES WR_SAFETY_ERR_PWM_HMAX_CFG (SPI WR update can occur only in the DIAGNOSTIC state)
80 0x61 — RD_SAFETY_ERR_PWM_HMAX_CFG
81 50 0x92 YES WR_SAFETY_ERR_PWM_HMIN_CFG (SPI WR update can occur only in the DIAGNOSTIC state)
82 0x62 — RD_SAFETY_ERR_PWM_HMIN_CFG
83 51 0x94 YES WR_SAFETY_ERR_PWM_LMAX_CFG (SPI WR update can occur only in the DIAGNOSTIC state)
84 0x64 — RD_SAFETY_ERR_PWM_LMAX_CFG
85 52 0x97 YES WR_SAFETY_ERR_PWM_LMIN_CFG (SPI WR update can occur only in the DIAGNOSTIC state)
86 0x67 — RD_SAFETY_ERR_PWM_LMIN_CFG
87 53 0x98 YES WR_SAFETY_PWD_TH_CFG (SPI WR update can occur only in the DIAGNOSTIC state)
88 0x68 — RD_SAFETY_PWD_TH_CFG
89 54 0x9B YES WR_SAFETY_DEV_CFG_CRC (SPI WR update can occur only in the DIAGNOSTIC state)
90 0x6B — RD_SAFETY_DEV_CFG_CRC
91 55 0x9D YES RESERVED
92 0x6D — RESERVED
93 56 0x9E YES RESERVED
94 0x6E — RESERVED
95 57 0xA1 YES RESERVED
96 0x71 — RESERVED
97 58 0xA2 YES RESERVED
98 0x72 — RESERVED
99 59 0xB7 YES WR_SPI_STORAGE_REGISTER1
100 0x74 — RD_SPI_STORAGE_REGISTER1
101 60 0xB8 YES WR_SPI_STORAGE_REGISTER2
102 0x77 — RD_SPI_STORAGE_REGISTER2
103 61 0xBE SPI control register commands NO WR_DIAG_CTRL
104 0x78 — RD_DIAG_CTRL
105 62 0x8B NO WR_DIAG_MUX_SEL
106 0x7B — RD_DIAG_MUX_SEL
107 63 0x8D SPI configuration register commands (with WR SW lock state controlled by SET_CTRL_LOCK and CLR_CTRL_LOCK commands) YES WR_WDT_WIN1_CFG (SPI WR update can occur only in the DIAGNOSTIC state)
108 0x7D — RD_WDT_WIN1_CFG
109 64 0x8E YES WR_WDT_WIN2_CFG (SPI WR update can occur only in the DIAGNOSTIC state)
110 0x7E — RD_WDT_WIN2_CFG
111 65 0xB1 YES WR_WDT_Q&A_CFG (SPI WR update can occur only in the DIAGNOSTIC state)
112 0x81 — RD_WDT_Q&A_CFG
113 66 0x82 Single SPI execution commands without associated memory-mapped register — RD_WDT_QUESTION_VALUE
114 67 0x84 — RD_WDT_STATUS
115 68 0xB2 NO WR_WDT_ANSWER
116 69 0x88 SPI status register commands — RD_OFF_STATE_L_STAT
117 0x04 Single SPI execution commands without associated memory-mapped register MASK_DIAG_EXIT
118 0x87 UNMASK_DIAG_EXIT
119 0xC8 EN_SAFE_TO
120 0xCB DIS_SAFE_TO
121 0xCD SAFE_EXIT