JAJSGN3C December   2018  – December 2022 TPS7A25

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
  7. 7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Output Enable
      2. 8.3.2 Dropout Voltage
      3. 8.3.3 Current Limit
      4. 8.3.4 Undervoltage Lockout (UVLO)
      5. 8.3.5 Thermal Shutdown
      6. 8.3.6 Power Good
      7. 8.3.7 Active Overshoot Pulldown Circuitry
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Functional Mode Comparison
      2. 8.4.2 Normal Operation
      3. 8.4.3 Dropout Operation
      4. 8.4.4 Disabled
        1.       Application and Implementation
          1. 9.1 Application Information
            1. 9.1.1 Adjustable Device Feedback Resistors
            2. 9.1.2 Recommended Capacitor Types
            3. 9.1.3 Input and Output Capacitor Requirements
            4. 9.1.4 Reverse Current
            5. 9.1.5 Feed-Forward Capacitor (CFF)
            6. 9.1.6 Power Dissipation (PD)
            7. 9.1.7 Estimating Junction Temperature
            8. 9.1.8 Special Consideration for Line Transients
          2. 9.2 Typical Application
            1. 9.2.1 Design Requirements
            2. 9.2.2 Detailed Design Procedure
              1. 9.2.2.1 Transient Response
              2. 9.2.2.2 Selecting Feedback Divider Resistors
              3. 9.2.2.3 Thermal Dissipation
            3. 9.2.3 Application Curve
          3. 9.3 Power Supply Recommendations
          4. 9.4 Layout
            1. 9.4.1 Layout Guidelines
            2. 9.4.2 Layout Examples
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DRV|6
サーマルパッド・メカニカル・データ
発注情報

8.3.6 Power Good

The power-good (PG) pin is an open-drain output and can be connected to a regulated supply through an external pullup resistor. The maximum pullup voltage is listed as VPG in the Recommended Operating Conditions table. For the PG pin to have a valid output, the voltage on the IN pin must be greater than VUVLO(RISING), as listed in the Electrical Characteristics table. When the VOUT exceeds VIT(PG,RISING), the PG output is high impedance and the PG pin voltage pulls up to the connected regulated supply. When the regulated output falls below VIT(PG,FALLING), the open-drain output turns on and pulls the PG output low after a short deglitch time. If output voltage monitoring is not needed, the PG pin can be left floating or connected to ground.

The recommended maximum PG pin sink current (IPG-SINK) and the leakage current into the PG pin (ILKG(PG)) are listed in the Electrical Characteristics table.

The PG pullup voltage (VPG_PULLUP), the desired minimum power-good output voltage (VPG(MIN)), and ILKG(PG) limit the maximum PG pin pullup resistor value (RPG_PULLUP). VPG_PULLUP, the PG pin low-level output voltage (VOL(PG)), and IPG-SINK limit the minimum RPG_PULLUP. Maximum and minimum values for RPG_PULLUP can be calculated from the following equations:

Equation 2. RPG_PULLUP(MAX) = (VPG_PULLUP – VPG(MIN)) / ILKG(PG)_MAX
Equation 3. RPG_PULLUP(MIN) = (VPG_PULLUP – VOL(PG)) / IPG-SINK

For example, if the PG pin is connected to a pullup resistor with a 3.3-V external supply, from Equation 2, RPG_PULLUP(MAX) is 11 MΩ. From Equation 3, RPG_PULLUP(MIN) is 5.8 kΩ.