JAJSDD4B July   2017  – January 2019 TPS7A92

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
      2.      代表的なアプリケーションの図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable
      2. 7.3.2 Dropout Voltage (VDO)
      3. 7.3.3 Output Voltage Accuracy
      4. 7.3.4 High Power-Supply Ripple Rejection (PSRR)
      5. 7.3.5 Low Output Noise
      6. 7.3.6 Output Soft-Start Control
      7. 7.3.7 Power-Good Function
      8. 7.3.8 Internal Protection Circuitry
        1. 7.3.8.1 Undervoltage Lockout (UVLO)
        2. 7.3.8.2 Internal Current Limit (ICL)
        3. 7.3.8.3 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Output
      2. 8.1.2 Start-Up
        1. 8.1.2.1 Enable (EN) and Undervoltage Lockout (UVLO)
        2. 8.1.2.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
          1. 8.1.2.2.1 Noise Reduction
          2. 8.1.2.2.2 Soft-Start and Inrush Current
      3. 8.1.3 Capacitor Recommendation
        1. 8.1.3.1 Input and Output Capacitor Requirements (CIN and COUT)
          1. 8.1.3.1.1 Load-Step Transient Response
        2. 8.1.3.2 Feed-Forward Capacitor (CFF)
      4. 8.1.4 Power Dissipation (PD)
      5. 8.1.5 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 評価モジュール
        2. 11.1.1.2 SPICEモデル
      2. 11.1.2 デバイスの項目表記
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over operating temperature range (TJ = –40°C to +125°C), VIN = 1.4 V, VOUT(TARGET) = 0.8 V, IOUT = 50 mA, VEN = 1.4 V, COUT = 22 μF, CNR/SS = 0 nF, CFF = 0 nF, SS_CTRL = GND, PG pin pulled up to VINx with 100 kΩ, and for each channel (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input supply voltage range 1.4 6.5 V
VREF Reference voltage 0.8 V
VUVLO Input supply UVLO VIN rising 1.31 1.39 V
VHYS VUVLO 290 mV
VOUT Output voltage range 0.8 – 1.0% 5.2 + 1.0% V
Output voltage accuracy(1)(2) 0.8 V ≤ VOUT ≤ 5 V, 5 mA ≤ IOUT ≤ 2 A –1.0% 1.0%
ΔVOUT(ΔVIN) Line regulation IOUT= 5 mA, 1.4 V ≤ VIN ≤ 6.5 V 0.003 %/V
ΔVOUT(ΔIOUT) Load regulation 5 mA ≤ IOUT ≤ 2 A 0.03 %/A
VDO Dropout voltage VIN ≥ 1.4 V, 0.8 V ≤ VOUT ≤ 5.0 V,
IOUT = 2 A, VFB = 0.8 V – 3%		 400 mV
ILIM Output current limit VOUT forced at 0.9 × VOUT(TARGET),
VIN = VOUT(TARGET) + 300 mV		 2.3 2.6 2.9 A
IGND GND pin current Both channels enabled, per channel,
VIN = 6.5 V, IOUT = 5 mA		 2.1 3.5 mA
Both channels enabled, per channel,
VIN = 1.4 V, IOUT = 2 A		 4
ISDN Shutdown GND pin current Both channels shutdown, per channel, PGx = (open),
VIN = 6.5 V, VEN = 0.5 V		 0.1 15 µA
IEN EN pin current VIN = 6.5 V, 0 V ≤ VEN ≤ 6.5 V –0.2 0.2 µA
VIL(EN) EN pin low-level input voltage (device disabled) 0 0.4 V
VIH(EN) EN pin high-level input voltage (device enabled) 1.1 6.5 V
ISS_CTRL SS_CTRL pin current VIN = 6.5 V, 0 V ≤ VSS_CTRL ≤ 6.5 V –0.2 0.2 µA
VIT(PG) PG pin threshold For PG transitioning low with falling VOUT, expressed as a percentage of VOUT(TARGET) 82% 88.9% 93%
Vhys(PG) PG pin hysteresis For PG transitioning high with rising VOUT, expressed as a percentage of VOUT(TARGET) 1%
VOL(PG) PG pin low-level output voltage VOUT < VIT(PG), IPG = –1 mA (current into device) 0.4 V
Ilkg(PG) PG pin leakage current VOUT > VIT(PG), VPG = 6.5 V 1 µA
INR/SS NR/SS pin charging current VNR/SS = GND, 1.4 V ≤ VIN ≤ 6.5 V,
VSS_CTRL = GND		 4.0 6.2 9.0 µA
VNR/SS = GND, 1.4 V ≤ VIN ≤ 6.5 V, VSS_CTRL = VIN 65 100 150
IFB FB pin leakage current VIN = 6.5 V, VFB = 0.8 V –100 100 nA
PSRR Power-supply ripple rejection f = 500 kHz, VINx = 2.0 V, VOUT = 1.2 V,
IOUT = 2 A, CNR/SS = 10 nF, CFF = 10 nF		 40 dB
Vn Output noise voltage BW = 10 Hz to 100 kHz, VIN = 1.8 V, VOUT = 0.8 V,
IOUT = 2.0 A, CNR/SS = 10 nF, CFF = 10 nF		 4.6 μVRMS
Noise spectral density f = 10 kHz, VIN = 1.8 V, VOUT = 0.8 V,
IOUT = 2.0 A, CNR/SS = 10 nF, CFF = 10 nF		 15 nV/√Hz
Rdiss Output active discharge resistance VEN = GND 250 Ω
Tsd Thermal shutdown temperature Shutdown, temperature increasing 160 °C
Reset, temperature decreasing 140
(1) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
(2) The device is not tested under conditions where VIN > VOUT + 2.5 V and IOUT = 2 A because the power dissipation is higher than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the power dissipation limit of the package under test.