JAJSDD4B July   2017  – January 2019 TPS7A92

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
      2.      代表的なアプリケーションの図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable
      2. 7.3.2 Dropout Voltage (VDO)
      3. 7.3.3 Output Voltage Accuracy
      4. 7.3.4 High Power-Supply Ripple Rejection (PSRR)
      5. 7.3.5 Low Output Noise
      6. 7.3.6 Output Soft-Start Control
      7. 7.3.7 Power-Good Function
      8. 7.3.8 Internal Protection Circuitry
        1. 7.3.8.1 Undervoltage Lockout (UVLO)
        2. 7.3.8.2 Internal Current Limit (ICL)
        3. 7.3.8.3 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Output
      2. 8.1.2 Start-Up
        1. 8.1.2.1 Enable (EN) and Undervoltage Lockout (UVLO)
        2. 8.1.2.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
          1. 8.1.2.2.1 Noise Reduction
          2. 8.1.2.2.2 Soft-Start and Inrush Current
      3. 8.1.3 Capacitor Recommendation
        1. 8.1.3.1 Input and Output Capacitor Requirements (CIN and COUT)
          1. 8.1.3.1.1 Load-Step Transient Response
        2. 8.1.3.2 Feed-Forward Capacitor (CFF)
      4. 8.1.4 Power Dissipation (PD)
      5. 8.1.5 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 評価モジュール
        2. 11.1.1.2 SPICEモデル
      2. 11.1.2 デバイスの項目表記
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.2.2.2 Soft-Start and Inrush Current

Soft-start refers to the gradual ramp-up characteristic of the output voltage after the EN and UVLO thresholds are exceeded. Reducing how quickly the output voltage increases during startup also reduces the amount of current needed to charge the output capacitor, referred to as inrush current. Inrush current is defined as the current going into the LDO during start-up. Inrush current consists of the load current, the current used to charge the output capacitor, and the ground pin current (that contributes very little to inrush current). This current is difficult to measure because the input capacitor must be removed, which is not recommended. However, the inrush current can be estimated by Equation 4:

Equation 4. TPS7A92 q_iout-t_sbvs282.gif

where

  • VOUT(t) is the instantaneous output voltage of the turn-on ramp
  • dVOUT(t)/dt is the slope of the VOUT ramp and
  • RLOAD is the resistive load impedance

The TPS7A92 features a monotonic, voltage-controlled soft-start that is set by the user with an external capacitor (CNR/SS). This soft-start helps reduce inrush current, minimizing load transients to the input power bus that can cause potential start-up initialization problems when powering FPGAs, digital signal processors (DSPs), or other high current loads.

To achieve a monotonic start-up, the TPS7A92 error amplifier tracks the voltage ramp of the external soft-start capacitor until the voltage exceeds approximately 97% of the internal reference. The final 3% of VNR/SS is charged through the noise-reduction resistor (RNR), creating an RC delay. RNR is approximately 280 kΩ and applications that require the highest accuracy when using a large value CNR/SS must take this RC delay into account.

The soft-start ramp time depends on the soft-start charging current (INR/SS), the soft-start capacitance (CNR/SS), and the internal reference (VREF). The approximate soft-start ramp time (tSS) can be calculated with Equation 5:

Equation 5. tSS = (VREF × CNR/SS) / INR/SS

The value for INR/SS is determined by the state of the SS_CTRL pin. When the SS_CTRL pin is connected to GND, the typical value for the INR/SS current is 6.2 µA. Connecting the SS_CTRL pin to IN increases the typical soft-start charging current to 100 µA. The larger charging current for INR/SS is useful if shorter start-up times are needed (such as when using a large noise-reduction capacitor).