JAJSDD4B July   2017  – January 2019 TPS7A92

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーション回路
      2.      代表的なアプリケーションの図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable
      2. 7.3.2 Dropout Voltage (VDO)
      3. 7.3.3 Output Voltage Accuracy
      4. 7.3.4 High Power-Supply Ripple Rejection (PSRR)
      5. 7.3.5 Low Output Noise
      6. 7.3.6 Output Soft-Start Control
      7. 7.3.7 Power-Good Function
      8. 7.3.8 Internal Protection Circuitry
        1. 7.3.8.1 Undervoltage Lockout (UVLO)
        2. 7.3.8.2 Internal Current Limit (ICL)
        3. 7.3.8.3 Thermal Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Adjustable Output
      2. 8.1.2 Start-Up
        1. 8.1.2.1 Enable (EN) and Undervoltage Lockout (UVLO)
        2. 8.1.2.2 Noise-Reduction and Soft-Start Capacitor (CNR/SS)
          1. 8.1.2.2.1 Noise Reduction
          2. 8.1.2.2.2 Soft-Start and Inrush Current
      3. 8.1.3 Capacitor Recommendation
        1. 8.1.3.1 Input and Output Capacitor Requirements (CIN and COUT)
          1. 8.1.3.1.1 Load-Step Transient Response
        2. 8.1.3.2 Feed-Forward Capacitor (CFF)
      4. 8.1.4 Power Dissipation (PD)
      5. 8.1.5 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Board Layout
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
        1. 11.1.1.1 評価モジュール
        2. 11.1.1.2 SPICEモデル
      2. 11.1.2 デバイスの項目表記
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.1.1 Adjustable Output

The output voltage of the TPS7A9201 can be adjusted from 0.8 V to 5.2 V by using a resistor divider network as shown in Figure 38.

TPS7A92 adj_cir_sbvs318.gifFigure 38. Adjustable Operation

R1 and R2 can be calculated for any output voltage range using Equation 3. This resistive network must provide a current greater than or equal to 5 μA for optimum noise performance.

Equation 3. TPS7A92 q_r1_sbvs282.gif

If greater voltage accuracy is required, take into account the output voltage offset contribution resulting from the feedback pin current (IFB) and use 0.1%-tolerance resistors.

Table 2 lists the resistor combination required to achieve a few of the most common rails using commercially-available, 0.1%-tolerance resistors to maximize nominal voltage accuracy and also abiding to the formula given in Equation 3.

Table 2. Recommended Feedback-Resistor Values

VOUT(TARGET)
(V)		 FEEDBACK RESISTOR VALUES (1) CALCULATED OUTPUT VOLTAGE (V)
R1 (kΩ) R2 (kΩ)
0.8 Short Open 0.800
1.00 2.55 10.2 1.000
1.20 5.9 11.8 1.200
1.50 9.31 10.7 1.496
1.80 1.87 1.5 1.797
1.90 15.8 11.5 1.899
2.50 2.43 1.15 2.490
3.00 3.16 1.15 2.998
3.30 3.57 1.15 3.283
5.00 10.5 2 5.00
(1) R1 is connected from OUT to FB; R2 is connected from FB to GND; see Figure 38.