SLUSBU2A September   2014  – February 2016 TPS92661-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Controlling the Internal LED Bypass Switches
      2. 7.3.2  Internal Switch Resistance
      3. 7.3.3  PWM Dimming
      4. 7.3.4  PWM Clock
      5. 7.3.5  PWM Synchronization
      6. 7.3.6  Switch Slew Control
      7. 7.3.7  Effect of Phase Shifting LED Duty Cycles
      8. 7.3.8  LED Fault Detection and Protection
        1. 7.3.8.1 Fault Reporting and Timing
          1. 7.3.8.1.1 LED Open Fault Detect Timing Example
      9. 7.3.9  Glitch-Free Operation
        1. 7.3.9.1 Atomic Multi-Byte Writes
        2. 7.3.9.2 Synchronous Updates
          1. 7.3.9.2.1 LEDxON = LEDxOFF Boundary Condition
      10. 7.3.10 Internal Oscillator and Watchdog Timers
        1. 7.3.10.1 Clock Watchdog Timer
        2. 7.3.10.2 Communications Watchdog Timer
    4. 7.4 Device Functional Modes
      1. 7.4.1  Digital Interface Connections
        1. 7.4.1.1  Address (ADR0, ADR1, and ADR2 Pins)
        2. 7.4.1.2  Clock (CLK Pin)
        3. 7.4.1.3  Internal Charge Pump (CPP Pin)
        4. 7.4.1.4  Enable (EN Pin)
        5. 7.4.1.5  GND Pin
        6. 7.4.1.6  Receive (RX Pin)
        7. 7.4.1.7  Synchronization (SYNC Pin)
        8. 7.4.1.8  Transmit (TX Pin)
        9. 7.4.1.9  Primary Power Supply (VIN Pin)
        10. 7.4.1.10 On-Board 3.3-V Supply (VCC Pin)
      2. 7.4.2  Internal Pin-to-Pin Resistance
      3. 7.4.3  UART Physical Layer
      4. 7.4.4  UART Clock and Baudrate
      5. 7.4.5  UART Communications Reset
      6. 7.4.6  UART Device Addressing
      7. 7.4.7  UART Communications Protocol
        1. 7.4.7.1 Example 1:
        2. 7.4.7.2 Example 2:
        3. 7.4.7.3 Example 3:
      8. 7.4.8  Transaction Frame Description
      9. 7.4.9  Frame Initialization Byte
      10. 7.4.10 Register Address
      11. 7.4.11 Data Bytes
      12. 7.4.12 CRC Bytes
      13. 7.4.13 Registers
        1. 7.4.13.1 LED ON Registers
        2. 7.4.13.2 LED OFF Registers
        3. 7.4.13.3 Alternate LED On/Off Registers
        4. 7.4.13.4 Enable Registers
        5. 7.4.13.5 Control Registers
          1. 7.4.13.5.1 PWM Clock Divider Register (PCKDIV)
          2. 7.4.13.5.2 System Configuration Register (SYSCFG)
        6. 7.4.13.6 Default LED State Register (DEFLED)
        7. 7.4.13.7 PWM Period Counter Register (TCNT)
        8. 7.4.13.8 Diagnostic Registers
    5. 7.5 Programming
      1. 7.5.1 Read / Write Register Flow Chart
        1. 7.5.1.1 Register Write Flow Chart
        2. 7.5.1.2 Register Read Flow Chart
      2. 7.5.2 Complete Transaction Example
      3. 7.5.3 CRC Calculation Programming Examples
      4. 7.5.4 Code Examples to Implement Register Reads/Writes
    6. 7.6 Register Map
  8. 8 Application and Implementation
    1. 8.1 Applications Information
      1. 8.1.1 Guidelines For Current Source
    2. 8.2 Design Examples
      1. 8.2.1 12 LED, 1.1-A Application
      2. 8.2.2 6 LED, 1.5-A Application
  9. 9 Power Supply Recommendations
    1. 9.1 General Recommendations
    2. 9.2 Internal Regulator
    3. 9.3 Power Up and Reset
    4. 9.4 VIN Power Consumption
    5. 9.5 Initialization Set-Up
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Export Control Notice
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings(1)(2)

Over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Input voltage VIN, VCC to GND –0.3 7 V
CPP to GND –0.3 67
CPP to LED12 –0.3 7
LEDx to GND –0.3 60
LEDx to LED(x-1) –0.3 7
SYNC, EN, CLK, TX, RX, ADR0-2 to GND –0.3 7
Storage temperature range, Tstg –40 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales/Office/Distributors for availability and specifications.

6.2 ESD Ratings

MIN MAX UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002 (1) –2000 2000 V
Charged device model (CDM), per AEC Q100-011 All Pins –750 750
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Supply input voltage range 4.5 5.5 V
VI Input voltage range per channel LEDx to LED(x-1) 5.0 V
IO Output current range LEDx to LED(x-1), continuous 2.0 A
LEDx to LED(x-1), pulsed, 1-ms duration 4.0
fCLK CLK frequency(1) 0.1 16 MHz
DCLK CLK duty cycle 40% 60%
tEW EN input pulse width low 50 ns
tESS EN setup to serial start 24/fCLK s
tSW SYNC input pulse width 1/fCLK s
VIH High-level input voltage 1.9 VVCC + 0.3 V V
VIL Low-level input voltage GND – 0.3 V 0.8 V
TA Ambient temperature –40 125 °C
TJ Junction temperature –40 150 °C
(1) Minimum fclk is applicable only when CKWEN bit is set. fclk as low as 0 Hz is possible when bit is not set.

6.4 Thermal Information

THERMAL METRIC(1) TPS92661-Q1 UNITS
TQFP (PHP)
48 Pins
RθJA Junction-to-ambient thermal resistance 25.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 10.5
RθJB Junction-to-board thermal resistance 6.1
ψJT Junction-to-top characterization parameter 0.2
ψJB Junction-to-board characterization parameter 6.0
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Limits apply over operating junction temperature range –40°C ≤ TJ ≤ +150°C. Typical values represent the most likely parametric norm at TJ = 25°C. Unless otherwise noted, VIN = 5 V. For digital outputs, CLOAD = 20 pF.
PARAMETER CONDITIONS MIN TYP MAX UNIT
GENERAL
IVIN-OP Input operating bias current No switching 1 mA
VIN-UVT VIN internal POR threshold VIN rising 4.5 V
VCC-REG Regulated VCC voltage 0 mA ≤ IVCC ≤ 5 mA 3.1 3.3 3.5 V
IVCC-LIM VCC current limit 10 mA
VCPP Charge pump operating voltage VVIN = 5 V, 0 V ≤ VSW ≤ –60 V 6.2 V
fCPP Charge pump oscillator frequency 1.3 2.3 3.3 MHz
LED MATRIX SWITCHES
RDS(on) LED switch on-resistance (2) 225 mΩ
RALL(on) All switches on-resistance Measured LED12 - LED0 1800 3400 mΩ
IDS(off) OFF state switch leakage current 50 µA
VTH-S LED short threshold voltage 0 V ≤ VSW ≤ –60 V 0.52 1.4 V
VTH-O LED OPEN threshold voltage 0 V ≤ VSW ≤ –60 V 5 6 6.9 V
tTO-O LED OPEN detection and correction delay 50 150 ns
tREP LED fault reporting delay 5 µs
tRISE(LEDx) LEDx drain voltage rise time(1) ILED = 800 mA 2 µs
tFALL(LEDx) LEDx drain voltage fall time(1) ILED = 800 mA 2 µs
DIGITAL SPECIFICATIONS
VIH-TH High-level input voltage threshold 1.9 V
VIL-TH Low-level input voltage threshold 0.8 V
VOH High-level output voltage ISOURCE = 2 mA, VVCC = 4.0 V 4.27 V
VOL Low-level output voltage ISINK = 2 mA, VVCC = 4.5 V 0.23 V
IOS Output short circuit current (source or sink) VVCC = 4.5 V 42 mA
RSP Internal SYNC pull-down 100 kΩ
tWD-TO CLK watchdog timeout 32/fCPP µs
tTO CLK rise to TX output valid(1) 80 ns
tTZ CLK rise to TX output tri-state(1) 80 ns
(1) Specified by design. Not production tested.
(2) Single channel on-resitance (RDS(on)) measurement includes internal bond wires. All switches on-resistance (RALL(on)) should be used for all power calculations. See Internal Switch Resistance for details.

6.6 Typical Characteristics

TA = 25°C free air unless otherwise specified
TPS92661-Q1 D010_SLUSBU2.gif
VVIN = 5.5 V fCLK = 6 MHz
Figure 1. Input Voltage Current vs Temperature
TPS92661-Q1 D012_SLUSBU2.gif
VVIN = 5.5 V fCLK = 15 MHz
Figure 3. Input Voltage Current vs Temperature
TPS92661-Q1 D016_SLUSBU2.gif
Figure 5. Regulated VCC Voltage vs Junction Temperature
TPS92661-Q1 D018_SLUSBU2.gif Figure 7. Charge Pump Oscillator Frequency vs Junction Temperature
TPS92661-Q1 D011_SLUSBU2.gif
VVIN = 5.5 V fCLK = 8.57 MHz
Figure 2. Input Voltage Current vs Temperature
TPS92661-Q1 D015_SLUSBU2.gif
Figure 4. Input Operating Bias Current, Non-Switching vs. Junction Temperature
TPS92661-Q1 D017_SLUSBU2.gif
Figure 6. All Switches On-Resistance vs Junction Temperature
TPS92661-Q1 D019_SLUSBU2.gif Figure 8. Channel Open and Short Protection Thresholds vs Junction Temperature