SLVSI15A March   2025  – December 2025 TPSM8287B15 , TPSM8287B30

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency DCS-Control Topology
      2. 7.3.2  Forced PWM and Power Save Modes
      3. 7.3.3  Precise Enable
      4. 7.3.4  Start-Up
      5. 7.3.5  Output Voltage Setting
        1. 7.3.5.1 Output Voltage Setpoint
        2. 7.3.5.2 Output Voltage Range
        3. 7.3.5.3 Non-Default Output Voltage Setpoint
        4. 7.3.5.4 Dynamic Voltage Scaling (DVS)
        5. 7.3.5.5 Droop Compensation
      6. 7.3.6  Compensation (COMP)
      7. 7.3.7  Mode Selection / Clock Synchronization (MODE/SYNC)
      8. 7.3.8  Spread Spectrum Clocking (SSC)
      9. 7.3.9  Output Discharge
      10. 7.3.10 Undervoltage Lockout (UVLO)
      11. 7.3.11 Overvoltage Lockout (OVLO)
      12. 7.3.12 Overcurrent Protection
        1. 7.3.12.1 Cycle-by-Cycle Current Limiting
        2. 7.3.12.2 Hiccup Mode
        3. 7.3.12.3 Current-Limit Mode
      13. 7.3.13 Power Good (PG)
        1. 7.3.13.1 Power-Good Standalone, Primary Device Behavior
        2. 7.3.13.2 Power-Good Secondary Device Behavior
      14. 7.3.14 Remote Sense
      15. 7.3.15 Thermal Warning and Shutdown
      16. 7.3.16 Stacked Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset (POR)
      2. 7.4.2 Undervoltage Lockout
      3. 7.4.3 Standby
      4. 7.4.4 On
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard-, Fast-, Fast-Mode Plus Protocol
      3. 7.5.3 I2C HS-Mode Protocol
      4. 7.5.4 I2C Update Sequence
      5. 7.5.5 I2C Register Reset
  9. 8 Device Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input Capacitors
        2. 9.2.2.2 Selecting the Target Loop Bandwidth
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.2.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application Using Two TPSM8287B30x in Parallel Operation
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Selecting the Input Capacitors
        2. 9.3.2.2 Selecting the Target Loop Bandwidth
        3. 9.3.2.3 Selecting the Compensation Resistor
        4. 9.3.2.4 Selecting the Output Capacitors
        5. 9.3.2.5 Selecting the Compensation Capacitor, CComp1
        6. 9.3.2.6 Selecting the Compensation Capacitor, CComp2
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
        1. 9.5.2.1 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.5.4 Dynamic Voltage Scaling (DVS)

If the user changes the output voltage setpoint while the device is operating, the device ramps up or down to the new voltage setting in a controlled way.

The VRAMP[1:0] bits in the CONTROL1 register set the slew rate when the device ramps from one voltage to another during DVS (see Table 7-4). The ramp rate is independent of the setting of the VRANGE[1:0] bits.

Table 7-4 Dynamic Voltage Scaling Slew Rate
VRAMP[1:0]DVS SLEW RATE
0b00 (default)10mV/μs
0b015mV/μs
0b101.25mV/μs
0b110.5mV/μs

If the MODE/SYNC pin is low and FPWMEN = 0, the slew rate can be less at low output currents because the device does not actively transfer energy back from the output capacitor to the input. At higher load currents the device controls the slew rate by transferring energy to the output.

Note that ramping the output to a higher voltage requires additional output current, so that during DVS the converter must generate a total output current given by:

Equation 4. I OUT = I OUT ( DC ) + C OUT × d V O U T dt

where:

  • IOUT is the total current the converter must generate while ramping to a higher voltage
  • IOUT(DC) is the DC load current
  • COUT is the total output capacitance
  • dVOUT/dt is the slew rate of the output voltage (programmable in the range 0.5mV/µs to 10mV/µs)

For correct operation, make sure that the total output current during DVS does not exceed the rated current of the device.