SLWS224E August   2010  – January 2016 TRF372017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics
    5. 6.5 Timing Requirements - SPI: Writing Phase
    6. 6.6 Timing Requirements - SPI: Read-Back Phase
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Integer and Fractional Mode Selection
      2. 7.3.2  Description of PLL Structure
        1. 7.3.2.1 Selecting PLL Divider Values
        2. 7.3.2.2 Setup Example for Integer Mode
        3. 7.3.2.3 Setup Example for Fractional Mode
      3. 7.3.3  Fractional Mode Setup
      4. 7.3.4  Selecting the VCO and VCO Frequency Control
      5. 7.3.5  External VCO
      6. 7.3.6  VCO Test Mode
      7. 7.3.7  Lock Detect
      8. 7.3.8  Tx Divider
      9. 7.3.9  LO Divider
      10. 7.3.10 Mixer
      11. 7.3.11 Disabling Outputs
      12. 7.3.12 Power Supply Distribution
      13. 7.3.13 Carrier Feedthrough Cancellation
      14. 7.3.14 Internal Baseband Bias Voltage Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Powersave Mode
    5. 7.5 Register Maps
      1. 7.5.1 Serial Interface Programming Registers Definition
        1. 7.5.1.1 PLL SPI Registers
          1. 7.5.1.1.1 Register 1
          2. 7.5.1.1.2 Register 2
          3. 7.5.1.1.3 Register 3
          4. 7.5.1.1.4 Register 4
          5. 7.5.1.1.5 Register 5
          6. 7.5.1.1.6 Register 6
          7. 7.5.1.1.7 Register 7
        2. 7.5.1.2 Readback Mode
          1. 7.5.1.2.1 Readback From the Internal Registers Banks
            1. 7.5.1.2.1.1 Register 0 Write
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 DAC Interfacing With External Baseband Bias Voltage
        2. 8.2.2.2 DAC Interface Using Internal VCM Generation
        3. 8.2.2.3 LO Outputs
        4. 8.2.2.4 Loop Filter
        5. 8.2.2.5 ESD Sensitivity
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10 Layout

10.1 Layout Guidelines

Layout of the application board significantly impacts the analog performance of the TRF372017 device. Noise and high-speed signals must be prevented from leaking onto power-supply pins or analog signals. Follow these recommendations:

  1. Place supply decoupling capacitors physically close to the device, on the same side of the board. Each supply pin must be isolated with a ferrite bead.
  2. Maintain a continuous ground plane in the vicinity of the device and as return paths for all high-speed signal lines. Place reference plane vias or decoupling capacitors near any signal line reference transition.
  3. The pad on the bottom of the device must be electrically grounded. Connect GND pins directly to the pad on the surface layer. Connect the GND pins and pad directly to surface ground where possible.
  4. Power planes must not overlap each other or high-speed signal lines.
  5. Isolate REF_IN routing from loop filter lines, control lines, and other high-speed lines.

See Figure 95 for an example of critical component layout (for the top PCB layer).

10.2 Layout Example

TRF372017 board_Layout_lws221.gif Figure 95. Critical Layout of the TRF372017 EVM Board