SBAS484 Data sheet

SBAS484B September 2010 – December 2016 TSC2014

PRODUCTION DATA.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

YZG|12
- MXBG028D

サーマルパッド・メカニカル・データ

発注情報

6 Electrical Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range (unless otherwise noted).

		MIN	MAX	UNIT
Voltage range	Analog input X+, Y+, AUX to GND	–0.4	V_DD + 0.1	V
	Analog input X–, Y– to GND	–0.4	V_DD + 0.1	V
	VDD/REF pin to GND	–0.	5	V
Digital input voltage to GND		–0.	V_DD + 0.3	V
Digital output voltage to GND		–0.	V_DD + 0.3	V
Operating free-air temperature range, T_A		–40	85	°C
Storage temperature range, T_STG		–65	150	°C
Junction temperature, T_J Max			150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Thermal Information

THERMAL METRIC⁽¹⁾		TSC2014	UNIT
		YZG (DSBGA)
		12 PINS
θ_JA	Junction-to-ambient thermal resistance	115	°C/W
θ_JCtop	Junction-to-case (top) thermal resistance	30	°C/W
θ_JB	Junction-to-board thermal resistance	82	°C/W
ψ_JT	Junction-to-top characterization parameter	5	°C/W
ψ_JB	Junction-to-board characterization parameter	75	°C/W
θ_JCbot	Junction-to-case (bottom) thermal resistance	—

(1)

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
	Power Supply, VDD/REF	1.2	3.3	3.6	V
T_A	Operating free-air temperature	–40		85	°C

6.5 Electrical Characteristics

At T_A = –40°C to +85°C, V_DD = +1.2V to +3.6V, unless otherwise noted.

PARAMETER		TEST CONDITIONS		TSC2014			UNIT
PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
AUXILIARY ANALOG INPUT
Input voltage range				0		VDD	V
Input capacitance					12		pF
Input leakage current				–1		+1	μA
Full-scale average input current		VDD = 1.6V, continuous AUX			2		μA
A/D CONVERTER
Resolution		Programmable: 10 or 12 bits				12	Bits
No missing codes		12-bit resolution		11			Bits
Integral linearity				–3	–0.6 to +0.38	+3	LSB⁽¹⁾
Differential linearity				–2	–0.46 to +0.49	+4	LSB
Offset error		V_DD = 1.6V		–5	0.53	+5	LSB
Gain error		V_DD = 1.6V		–3	0.32	+3	LSB
TOUCH SENSORS
PENIRQ 50kΩ pull-up resistor, R_IRQ		T_A = +25°C, V_DD = 1.6V			50		kΩ
X, Y drivers on-resistance	Y+, X+	T_A = +25°C, V_DD = 1.6V			6		Ω
X, Y drivers on-resistance	Y–, X–	T_A = +25°C, V_DD = 1.6V			4.5		Ω
X, Y drivers drive current⁽²⁾		100ms duration				50	mA
INTERNAL TEMPERATURE SENSOR
Temperature range				–40		+85	°C
Resolution		Differential method⁽³⁾	V_DD = 1.6V		0.3		°C/LSB
		Differential method⁽³⁾	V_DD = 3V		1.6		°C/LSB
		TEMP1⁽⁴⁾	V_DD = 1.6V		0.3		°C/LSB
		TEMP1⁽⁴⁾	V_DD = 3V		1.6		°C/LSB
Accuracy		Differential method⁽³⁾	V_DD = 1.6V		±3		°C/LSB
		Differential method⁽³⁾	V_DD = 3V		±2		°C/LSB
		TEMP1⁽⁴⁾	V_DD = 1.6V		±3		°C/LSB
		TEMP1⁽⁴⁾	V_DD = 3V		±2		°C/LSB
INTERNAL OSCILLATOR
Clock frequency, f_OSC		V_DD = 1.2V, T_A = +25°C			3.3		MHz
		V_DD = 1.6V		3.3	3.82	4.3	MHz
		V_DD = 3.0V, T_A = +25°C			4.1		MHz
Frequency drift		V_DD = 1.2V			0.121		%/°C
		V_DD = 1.6V			–0.013		%/°C
		V_DD = 3.0V			–0.028		%/°C
DIGITAL INPUT/OUTPUT
Logic family				CMOS
Logic level	V_IH	1.2V ≤ V_DD < 1.6V		0.7 × V_DD		V_DD + 0.3	V
	V_IH	1.6V ≤ V_DD ≤ 3.6V		0.7 × V_DD		V_DD + 0.3	V
	V_IL	1.2V ≤ V_DD < 1.6V		–0.3		0.2 × V_DD	V
	V_IL	1.6V ≤ V_DD ≤ 3.6V		–0.3		0.3 × V_DD	V
	I_IL	SCL and SDA pins		–1		1	μA
	C_IN	SCL and SDA pins				10	pF
	V_OH	I_OH = 2 TTL loads		V_DD – 0.2		V_DD	V
	V_OL	I_OL = 2 TTL loads		0		0.2	V
	I_LEAK	Floating output		–1		1	μA
	C_OUT	Floating output				10	pF
Data format				Straight Binary
POWER-SUPPLY REQUIREMENTS
Power-supply voltage
V_DD		Specified performance		1.2		3.6	V
Quiescent supply current ⁽⁵⁾		Filter off, M = W = 1, C[3:0] = (1,0,0,0), RM = 1, CL[1:0] = (0,1), cont AUX mode, f_ADC = 2MHz, without reading data register	V_DD = 1.6V		420	570	μA
		T_A = +25°C, filter on, M = 15, W = 7, PSM = 1, C[3:0] = (0,0,0,0), RM = 1, CL[1:0] = (0,1), BTD[2:0] = (1,0,1), 50SSPS, MAVEX = MAVEY = MAVEZ = 1, f_ADC = 2MHz, High-Speed mode, sensor drivers supply included⁽⁶⁾	V_DD = 1.2V		156		μA
			V_DD = 1.6V		200		μA
			V_DD = 3.0V		400		μA
		T_A = +25°C, filter off, M = W = 1, PSM = 1, C[3:0] = (0,0,0,0), RM = 1, CL[1:0] = (0,1), BTD[2:0] = (1,0,1), 50SSPS, MAVEX = MAVEY = MAVEZ = 1, f_ADC = 2MHz, High-Speed mode, sensor drivers supply included⁽⁶⁾	V_DD = 1.2V		140		μA
			V_DD = 1.6V		180		μA
			V_DD = 3.0V		370		μA
		T_A = +25°C, filter off, M = W = 1, C[3:0] = (0,1,0,1), RM = 1, CL[1:0] = (0,1), non-cont AUX mode, f_ADC = 2MHz, High-Speed mode	V_DD = 1.2V, ~27.2kSPS effective rate		150		μA
			V_DD = 1.6V, ~28.6kSPS effective rate		200		μA
			V_DD = 3.0V, ~29.1kSPS effective rate		390		μA
		T_A = +25°C, filter on, M = 7, W = 3, C[3:0] = (0,1,0,1), RM = 1, CL[1:0] = (0,1), MAVEAUX = 1, non-cont AUX mode, f_ADC = 2MHz, High-Speed mode, full speed	V_DD = 1.2V, ~10.3kSPS effective rate		272		μA
			V_DD = 1.6V, ~11.8kSPS effective rate		365		μA
			V_DD = 3.0V, ~12.3kSPS effective rate		683		μA
		T_A = +25°C, filter on, M = 7, W = 3, C[3:0] = (0,1,0,1), RM = 1, CL[1:0] = (0,1), MAVEAUX = 1, non-cont AUX mode, f_ADC = 2MHz, High-Speed mode, reduced speed (8.2kSPS equivalent rate)	V_DD = 1.2V, ~1.17kSPS effective rate		30.9		μA
			V_DD = 1.6V, ~1.17kSPS effective rate		36.2		μA
			V_DD = 3.0V, ~1.17kSPS effective rate		64.9		μA
Power-down supply current		T_A = +25°C, Not addressed, SCL = SDA = 1, V_DD = 1.6V, RESET = 1, PINTDAV = 1			0.023	0.8	μA

(1) LSB means Least Significant Bit. With V_REF = +2.5V, one LSB is 610μV.

(2) Assured by design, but not tested. Exceeding 50mA source current may result in device degradation.

(3) Difference between TEMP1 and TEMP2 measurement; no calibration necessary.

(4) Temperature drift is –2.1mV/°C, TEMP2 drift is –1.7mV/°C.

(5) For detailed information on test condition parameter and bit settings, see the section.

(6) Touch sensor modeled by: 2kΩ for X-plane and Y-plane, and 1kΩ for Z (touch resistance).

6.6 Timing Requirements for Figure 1: I²C Standard Mode (f_SCL = 100 kHz)

All specifications typical at –40°C to +85°C, V_DD = +1.2V to +3.6V, unless otherwise noted.

TWO-WIRE STANDARD MODE PARAMETERS		TEST CONDITIONS	MIN	MAX	UNIT
Reset low time⁽¹⁾	t_WL(RESET)	V_DD ≥ 1.6V	10		μs
Reset low time⁽¹⁾	t_WL(RESET)	1.2V ≤ V_DD < 1.6V	13		μs
SCL clock frequency	f_SCL			100	kHz
Bus free time between a STOP and START condition	t_BUF		4.7		μs
Hold time (repeated) START condition	t_{HD, STA}		4.0		μs
Low period of SCL clock	t_LOW		4.7		μs
High period of the SCL clock	t_HIGH		4.0		μs
Setup time for a repeated START condition	t_{SU, STA}		4.7		μs
Data hold time	t_{HD, DAT}		0	3.45	μs
Data setup time	t_{SU, DAT}		250		ns
Rise time of both SDA and SCL signals	t_R	C_b = total bus capacitance		1000	ns
Fall time of both SDA and SCL signals	t_F	C_b = total bus capacitance		300	ns
Setup time for STOP condition	t_{SU, STO}		4.0		μs
Capacitive load for each bus line	C_b	C_b = total capacitance of one bus line in pF		400	pF
Pulse width of spike suppressed	t_SP		N/A	N/A	ns

(1) Refer to Figure 36.

6.7 Timing Requirements for Figure 1: I²C Fast Mode (f_SCL = 400 kHz)

All specifications typical at –40°C to +85°C, V_DD = +1.2V to +3.6V, unless otherwise noted.

TWO-WIRE FAST MODE PARAMETERS		TEST CONDITIONS	MIN	MAX	UNIT
Reset low time⁽¹⁾	t_WL(RESET)	V_DD ≥ 1.6V	10		μs
Reset low time⁽¹⁾	t_WL(RESET)	1.2V ≤ V_DD < 1.6V	13		μs
SCL clock frequency	f_SCL			400	kHz
Bus free time between a STOP and START condition	t_BUF		1.3		μs
Hold time (repeated) START condition	t_{HD, STA}		0.6		μs
Low period of SCL clock	t_LOW		1.3		μs
High period of the SCL clock	t_HIGH		0.6		μs
Setup time for a repeated START condition	t_{SU, STA}		0.6		μs
Data hold time	t_{HD, DAT}		0	0.9	μs
Data setup time	t_{SU, DAT}		100		ns
Rise time of both SDA and SCL signals	t_R	C_b = total bus capacitance	20 + 0.1 × C_b	300	ns
Fall time of both SDA and SCL signals⁽²⁾	t_F	C_b = total bus capacitance	20 + 0.1 × C_b	300	ns
Setup time for STOP condition	t_{SU, STO}		0.6		μs
Capacitive load for each bus line	C_b	C_b = total capacitance of one bus line in pF		400	pF
Pulse width of spike suppressed	t_SP		0	50	ns

(1) Refer to Figure 36.

(2) C_b = the total capacitance of one bus line in pF. If using both Fast mode and Hs-mode devices, faster fall times according to the 3.4MHz High-Speed Mode table are allowed. Note that the TSC2014 is a Hs-mode device and follows the I²C, 3.4MHz, High-Speed Mode table requirements.

6.8 Timing Requirements for Figure 2: I²C High-Speed Mode (f_SCL = 1.7 MHz)

All specifications typical at –40°C to +85°C, V_DD = +1.2V to +3.6V, unless otherwise noted.

TWO-WIRE HIGH-SPEED MODE PARAMETERS		TEST CONDITIONS	MIN	MAX	UNIT
Reset low time⁽¹⁾	t_WL(RESET)	V_DD ≥ 1.6V	10		μs
Reset low time⁽¹⁾	t_WL(RESET)	1.2V ≤ V_DD < 1.6V	13		μs
SCL clock frequency	f_SCL			1.7	MHz
Hold time (repeated) START condition	t_{HD, STA}		160		ns
Low period of SCL clock	t_LOW		320		ns
High period of the SCL clock	t_HIGH		120		ns
Setup time for a repeated START condition	t_{SU, STA}		160		ns
Data hold time	t_{HD, DAT}		0	150	ns
Data setup time	t_{SU, DAT}		10		ns
Rise time of SCL signal	t_RCL	C_b = total bus capacitance⁽²⁾	20	80	ns
Rise time of SDA signal	t_RDA	C_b = total bus capacitance⁽²⁾	20	160	ns
Fall time of SCL signal	t_FCL	C_b = total bus capacitance⁽²⁾	20	80	ns
Fall time of SDA signal	t_FDA	C_b = total bus capacitance⁽²⁾	1	160	ns
Rise time of SCL signal after a repeated START condition and after an acknowledge bit	t_RCL1	C_b = total bus capacitance⁽²⁾	20	160	ns
Setup time for STOP condition	t_{SU, STO}		160		ns
Capacitive load for each bus line	C_b	C_b = total capacitance of one bus line in pF		400	pF
Pulse width of spike suppressed	t_SP		0	10	ns

(1) Refer to Figure 36.

(2) For capacitive bus loads between 100pF and 400pF, the rise and fall time values must be linearly interpolated.

6.9 Timing Requirements for Figure 2: I²C High-Speed Mode (f_SCL = 3.4 MHz)

All specifications typical at –40°C to +85°C, V_DD = +1.2V⁽²⁾ to +3.6V, unless otherwise noted.

TWO-WIRE HIGH-SPEED MODE PARAMETERS		TEST CONDITIONS	MIN	MAX	UNIT
Reset low time⁽¹⁾	t_WL(RESET)	V_DD ≥ 1.6V	10		μs
Reset low time⁽¹⁾	t_WL(RESET)	1.2V ≤ V_DD < 1.6V	13		μs
SCL clock frequency	f_SCL			3.4	MHz
Hold time (repeated) START condition	t_{HD, STA}		160		ns
Low period of SCL clock	t_LOW		160		ns
High period of the SCL clock	t_HIGH		60		ns
Setup time for a repeated START condition	t_{SU, STA}		160		ns
Data hold time	t_{HD, DAT}		0	70	ns
Data setup time	t_{SU, DAT}		10		ns
Rise time of SCL signal	t_RCL	C_b = total bus capacitance⁽³⁾	10	40	ns
Rise time of SDA signal	t_RDA	C_b = total bus capacitance⁽³⁾	10	80	ns
Fall time of SCL signal	t_FCL	C_b = total bus capacitance⁽³⁾	10	40	ns
Fall time of SDA signal	t_FDA	C_b = total bus capacitance⁽³⁾	1	80	ns
Rise time of SCL signal after a repeated START condition and after an acknowledge bit	t_RCL1	C_b = total bus capacitance⁽³⁾	10	80	ns
Setup time for STOP condition	t_{SU, STO}		160		ns
Capacitive load for each bus line	C_b	C_b = total capacitance of one bus line in pF		100	pF
Pulse width of spike suppressed	t_SP		0	10	ns

(1) Refer to Figure 36.

(2) Because of the low supply voltage of 1.2V and the wide temperature range of –40°C to +85°C, the I²C system devices may not reach the maximum specification of I²C High-Speed mode, and f_SCL may not reach 3.4MHz.

(3) Capacitive load from 10pF to 100pF.

6.10 Timing Information

Figure 1. Detailed I/O Timing for Standard and Fast Modes

Figure 2. Detailed I/O Timing for High-Speed Mode

6.11 Typical Characteristics

At T_A = –40°C to +85°C, V_DD = +1.2V to +3.6V, f_ADC = f_OSC/2,High-Speed mode (f_SCL = 3.4MHz), 12-bit mode, and non-continuous AUX measurement, unless otherwise noted.