JAJSHW8B september   2019  – october 2020 UCC23313

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Function
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  電力定格
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  安全限界値
    9. 6.9  Electrical Characteristics
    10. 6.10 スイッチング特性
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay, rise time and fall time
    2. 7.2 IOH and IOL testing
    3. 7.3 CMTI Testing
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supply
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
      4. 8.3.4 Protection Features
        1. 8.3.4.1 Undervoltage Lockout (UVLO)
        2. 8.3.4.2 Active Pulldown
        3. 8.3.4.3 Short-Circuit Clamping
    4. 8.4 Device Functional Modes
      1. 8.4.1 ESD Structure
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Input Resistor
        2. 9.2.2.2 Gate Driver Output Resistor
        3. 9.2.2.3 Estimate Gate-Driver Power Loss
        4. 9.2.2.4 Estimating Junction Temperature
        5. 9.2.2.5 Selecting VCC Capacitor
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 PCB Material
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
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発注情報

9.2.2.2 Gate Driver Output Resistor

The external gate-driver resistors, RG(ON) and RG(OFF) are used to:

  1. Limit ringing caused by parasitic inductances and capacitances
  2. Limit ringing caused by high voltage or high current switching dv/dt, di/dt, and body-diode reverse recovery
  3. Fine-tune gate drive strength, specifically peak sink and source current to optimize the switching loss
  4. Reduce electromagnetic interference (EMI)

The output stage has a pull up structure consisting of a P-channel MOSFET and an N-channel MOSFET in parallel. The combined peak source current is 4.5 A Use Equation 1 to estimate the peak source current as an example.

Equation 1. GUID-01F7E620-9F8B-4AD0-AEDF-28C6E88963C3-low.gif

where

  • RGON is the external turnon resistance.
  • RGFET_Int is the power transistor internal gate resistance, found in the power transistor data sheet. We will assume 0Ω for our example
  • IOH is the peak source current which is the minimum value between 4.5A, the gate-driver peak source current, and the calculated value based on the gate-drive loop resistance.
  • VGDF is the forward voltage drop for each of the diodes in series with RGON and RGOFF. The diode drop for this example is 0.7 V.

In this example, the peak source current is approximately 1.7A as calculated in Equation 2.

Equation 2. GUID-F4B4D73A-F3D0-4212-B995-CCA252CCD0C5-low.gif

Similarly, use Equation 3 to calculate the peak sink current.

Equation 3. GUID-1FC8679E-ED29-4459-9AB9-0E9741106457-low.gif

where

  • RGOFF is the external turnoff resistance.
  • IOL is the peak sink current which is the minimum value between 5.3A, the gate-driver peak sink current, and the calculated value based on the gate-drive loop resistance.

In this example, the peak sink current is the minimum of Equation 4 and 1.38A.

Equation 4. GUID-64775528-ECBF-4072-9FA4-8D1038F82EF6-low.gif

The diodes shown in series with each, RGON and RGOFF, in Figure 9-1 ensure the gate drive current flows through the intended path, respectively, during turn-on and turn-off. Note that the diode forward drop will reduce the voltage level at the gate of the power switch. To achieve rail-to-rail gate voltage levels, add a resistor from the VOUT pin to the power switch gate, with a resistance value approximately 20 times higher than RGON and RGOFF. For the examples described in this section, a good choice is 100 Ω to 200 Ω.

Note:

The estimated peak current is also influenced by PCB layout and load capacitance. Parasitic inductance in the gate-driver loop can slow down the peak gate-drive current and introduce overshoot and undershoot. Therefore, TI strongly recommends that the gate-driver loop should be minimized. Conversely, the peak source and sink current is dominated by loop parasitics when the load capacitance (CISS) of the power transistor is very small (typically less than 1 nF) because the rising and falling time is too small and close to the parasitic ringing period.