JAJSFJ9B December   2017  – October 2019 UCC28064A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Principles of Operation
      2. 8.3.2  Natural Interleaving
      3. 8.3.3  On-Time Control, Maximum Frequency Limiting, Restart Timer and Input Voltage Feed-Forward compensation
      4. 8.3.4  Distortion Reduction
      5. 8.3.5  Zero-Current Detection and Valley Switching
      6. 8.3.6  Phase Management and Light-Load Operation
      7. 8.3.7  Burst Mode Operation
      8. 8.3.8  External Disable
      9. 8.3.9  Improved Error Amplifier
      10. 8.3.10 Soft Start
      11. 8.3.11 Brownout Protection
      12. 8.3.12 Line Dropout Detection
      13. 8.3.13 VREF
      14. 8.3.14 VCC
      15. 8.3.15 System Level Protections
        1. 8.3.15.1 Failsafe OVP - Output Over-voltage Protection
        2. 8.3.15.2 Overcurrent Protection
        3. 8.3.15.3 Open-Loop Protection
        4. 8.3.15.4 VCC Undervoltage Lock-Out (UVLO) Protection
        5. 8.3.15.5 Phase-Fail Protection
        6. 8.3.15.6 CS - Open, TSET - Open and Short Protection
        7. 8.3.15.7 Thermal Shutdown Protection
        8. 8.3.15.8 Fault Logic Diagram
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Inductor Selection
        3. 9.2.2.3  ZCD Resistor Selection RZA, RZB
        4. 9.2.2.4  HVSEN
        5. 9.2.2.5  Output Capacitor Selection
        6. 9.2.2.6  Selecting RS For Peak Current Limiting
        7. 9.2.2.7  Power Semiconductor Selection (Q1, Q2, D1, D2)
        8. 9.2.2.8  Brownout Protection
        9. 9.2.2.9  Converter Timing
        10. 9.2.2.10 Programming VOUT
        11. 9.2.2.11 Voltage Loop Compensation
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Input Ripple Current Cancellation with Natural Interleaving
        2. 9.2.3.2 Brownout Protection
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Package Option Addendum
    1. 12.1 Packaging Information
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 開発サポート
        1. 13.1.1.1 WEBENCH®ツールによるカスタム設計
    2. 13.2 ドキュメントのサポート
      1. 13.2.1 関連資料
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 コミュニティ・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.3.3 On-Time Control, Maximum Frequency Limiting, Restart Timer and Input Voltage Feed-Forward compensation

Gate-drive on-time varies proportionately with the error-amplifier output voltage (VCOMP) and inversely proportional to the squared value of the peak of the rectified input voltage sensed through VINAC pin as stated by equation (3). In equation (3) it is shown that the on-time is inversely proportionally to the value of resistor RTSET connected between pin TSET and pin AGND. In order to calculate on-time, Equation (4) can be used. Parameter KT is function of the rectified peak input voltage sensed by pin VINAC as reported in graph of Figure 16. In this graph 3 curves are reported for three different values of RTSET. Two values of parameter KT are reported in the electrical specs table for two values of VINAC: KTL and KTH corresponding at the VINAC = 1.6V and VINAC = 5V and RTSET = 133kΩ. Because voltage on VINAC is proportional to the line rectified voltage, for tON calculation purposes we refer to the peak value of this voltage that is obtained through an internal peak detect. KT is inversely proportional to the squared value of VINAC peak value so it is the tON time realizing the so called voltage feed-forward compensation. The Voltage Feed-forward function modifies the MOSFET on time according to line voltage so, ideally output power delivered does not change if line voltage changes. When operating in single phase mode KT is called KTS and its value is doubled.

Equation 3. UCC28064A eq_ton1_slusde9.gif

The COMP pin voltage value is clamped at 4.95 V, so the maximum on time can be calculated by Equation 4.

Equation 4. UCC28064A eq_tom2_slusde9.gif

Figure 16 shows the values of KT versus the peak voltage value on VINAC pin.

The maximum switching frequency of each phase is limited by minimum-period timers. If the inductor current decays to zero before the minimum-period timer elapses, the next turn on will be delayed, resulting in discontinuous phase current.

A restart timer ensures starting under all circumstances by restarting both phases if the ZCD input of either phase has not transitioned from high-to-low within approximately 210 µs.

The minimum switching period, T(MIN), is inversely proportional to the time-setting resistor RTSET (the resistor from the TSET pin to ground).

UCC28064A D0123471.gifFigure 16. KT vs Peak Voltage