JAJSTC9A December   2023  – March 2024 UCC57108-Q1

ADVMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stage
      2. 6.3.2 Enable Function
      3. 6.3.3 Driver Stage
      4. 6.3.4 Desaturation (DESAT) Protection
      5. 6.3.5 Fault (FLT)
    4. 6.4 Device Functional Modes
  8. 7  Applications and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 VDD Undervoltage Lockout
      3. 7.2.3 Application Curves
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 サード・パーティ製品に関する免責事項
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • D|8
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-20231213-SS0I-PNKZ-ZKGD-LJ94GR5VBS9F-low.svg Figure 4-1 UCC5710xB-Q1 D Package SOIC-8 Top View
GUID-20231213-SS0I-LSQ3-CPC0-VD4LKP68PHCF-low.svg Figure 4-2 UCC5710xC-Q1 D Package SOIC-8 Top View
GUID-20231213-SS0I-7TQC-F0RG-8M6RJV3C2WF4-low.svg Figure 4-3 UCC5710xW-Q1 D Package SOIC-8 Top View
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME UCC5710xB-Q1 UCC5710xC-Q1 UCC5710xW-Q1
IN 1 1 1 I Non-inverting PWM input
VREF 2 2 NA O 5V Reference generated within the driver
NC NA NA 2 Not Connected
FLTb 3 3 3 O Active low fault reporting
DEAST 4 4 4 I Input for detecting the desatuation fault
VDD 5 5 5 P Driver bias supply
OUT 6 NA 6 O Output of the driver
OUTH NA 6 NA O Driver high output
EN NA NA 6 I Enable or disable control pin.
OUTL NA 7 NA O Driver low output
GND 7 8 8 G Driver ground
VEE 8 NA NA P Driver negtive bias supply with respect to GND
(1) I/O = Digital input/output, IA = Analog input, AO= Analog output, P = Power connection