JAJSH44C April   2011  – March  2019 UCD90120A

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     概略回路図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C/SMBus/PMBus Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TI Fusion GUI
      2. 7.3.2 PMBus Interface
      3. 7.3.3 Rail Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power-Supply Sequencing
        1. 7.4.1.1 Turn-On Sequencing
        2. 7.4.1.2 Turn-Off Sequencing
        3. 7.4.1.3 Sequencing Configuration Options
      2. 7.4.2  Pin-Selected Rail States
      3. 7.4.3  Monitoring
        1. 7.4.3.1 Voltage Monitoring
        2. 7.4.3.2 Current Monitoring
        3. 7.4.3.3 Remote Temperature Monitoring and Internal Temperature Sensor
        4. 7.4.3.4 Temperature by Host Input
      4. 7.4.4  Fault Responses and Alert Processing
      5. 7.4.5  Shut Down All Rails and Sequence On (Resequence)
      6. 7.4.6  GPIOs
      7. 7.4.7  GPO Control
      8. 7.4.8  GPO Dependencies
      9. 7.4.9  GPO Delays
      10. 7.4.10 State Machine Mode Enable
      11. 7.4.11 GPI Special Functions
      12. 7.4.12 Power-Supply Enables
      13. 7.4.13 Cascading Multiple Devices
      14. 7.4.14 PWM Outputs
        1. 7.4.14.1 FPWM1-8
        2. 7.4.14.2 PWM1-4
      15. 7.4.15 Programmable Multiphase PWMs
      16. 7.4.16 Margining
        1. 7.4.16.1 Open-Loop Margining
        2. 7.4.16.2 Closed-Loop Margining
      17. 7.4.17 System Reset Signal
      18. 7.4.18 Watch Dog Timer
      19. 7.4.19 Run Time Clock
      20. 7.4.20 Data and Error Logging to Flash Memory
      21. 7.4.21 Brownout Function
      22. 7.4.22 PMBus Address Selection
    5. 7.5 Programming
      1. 7.5.1 Device Configuration and Programming
        1. 7.5.1.1 Full Configuration Update While in Normal Mode
      2. 7.5.2 JTAG Interface
      3. 7.5.3 Internal Fault Management and Memory Error Correction (ECC)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Estimating ADC Reporting Accuracy
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Overview

Electronic systems that include CPU, DSP, microcontroller, FPGA, ASIC, and so forth, can have multiple voltage rails and require certain power on/off sequences in order to function correctly. The UCD90120A can control up to 12 voltage rails and ensure correct power sequences during normal condition and fault conditions.

In addition to sequencing, UCD90120A can continuously monitor rail voltages, currents, temperatures, fault conditions, and report the system health information to a PMBus host, improving systems’ long term reliability.

Also, the UCD90120A can protect electronic systems by responding to power system faults. The fault responses are conveniently configured by users through Fusion GUI. Fault events are stored in on-chip nonvolatile flash memory with time stamp in order to assist failure analysis.

System reliability can be improved through four-corner testing during system verification. During four-corner testing, each voltage rail is required to operate at the minimum and maximum output voltages, commonly known as margining. UCD90120A can perform closed-loop margining for up to 10 voltage rails. During normal operation, UCD90120A can also actively trim DC output voltages using the same margining circuitry.

The UCD90120A supports both PMBus- and pin-based control environments. UCD90120A functions as a PMBus slave. It can communicate with PMBus host with PMBus commands, and control voltage rails accordingly. Also, UCD90120A can be controlled by up to 8 GPIO configured GPI pins. The GPIs can be used as Boolean logic input to control up to 12 Logic GPO outputs. Each Logic GPO has a flexible Boolean logic builder. Input signals of the Boolean logic builder can include GPIs, other Logic GPO outputs, and selectable system flags such as POWER_GOOD, faults, warnings, etc. A simple state machine is also available for each Logic GPO pin.

The UCD90120A provides additional features such as pin-selected states, system watchdog, system reset, runtime clock, peak value log, reset counter, and so on. Pin-selected states feature allows users to use up to 3 GPIs to define up to 8 rail states. These states can implement system low-power modes as set out in the Advanced Configuration and Power Interface (ACPI) specification. Other features will be introduced in the following sections of this data sheet.