JAJSH44C April   2011  – March  2019 UCD90120A


  1. 特長
  2. アプリケーション
  3. 概要
    1.     概略回路図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C/SMBus/PMBus Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 TI Fusion GUI
      2. 7.3.2 PMBus Interface
      3. 7.3.3 Rail Configuration
    4. 7.4 Device Functional Modes
      1. 7.4.1  Power-Supply Sequencing
        1. Turn-On Sequencing
        2. Turn-Off Sequencing
        3. Sequencing Configuration Options
      2. 7.4.2  Pin-Selected Rail States
      3. 7.4.3  Monitoring
        1. Voltage Monitoring
        2. Current Monitoring
        3. Remote Temperature Monitoring and Internal Temperature Sensor
        4. Temperature by Host Input
      4. 7.4.4  Fault Responses and Alert Processing
      5. 7.4.5  Shut Down All Rails and Sequence On (Resequence)
      6. 7.4.6  GPIOs
      7. 7.4.7  GPO Control
      8. 7.4.8  GPO Dependencies
      9. 7.4.9  GPO Delays
      10. 7.4.10 State Machine Mode Enable
      11. 7.4.11 GPI Special Functions
      12. 7.4.12 Power-Supply Enables
      13. 7.4.13 Cascading Multiple Devices
      14. 7.4.14 PWM Outputs
        1. FPWM1-8
        2. PWM1-4
      15. 7.4.15 Programmable Multiphase PWMs
      16. 7.4.16 Margining
        1. Open-Loop Margining
        2. Closed-Loop Margining
      17. 7.4.17 System Reset Signal
      18. 7.4.18 Watch Dog Timer
      19. 7.4.19 Run Time Clock
      20. 7.4.20 Data and Error Logging to Flash Memory
      21. 7.4.21 Brownout Function
      22. 7.4.22 PMBus Address Selection
    5. 7.5 Programming
      1. 7.5.1 Device Configuration and Programming
        1. Full Configuration Update While in Normal Mode
      2. 7.5.2 JTAG Interface
      3. 7.5.3 Internal Fault Management and Memory Error Correction (ECC)
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Estimating ADC Reporting Accuracy
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 コミュニティ・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報



Design Requirements

1. TRST pin must have a 10-kΩ pulldown resistor to ground.

2. RESET pin must have a 10-kΩ pullup resistor to V33D and a 1-nF decoupling capacitor to ground. The components must be placed as close to the RESET pin as possible.

3. Depending on application environment, the PMBus signal integrity may be compromised at times. This causes the UCD90120A to receive incorrect PMBus commands. In a particular case, if (D9h) ROM_MODE command is erroneously received by a UCD90120A device, it causes the device to enter ROM mode; in this mode the device does not function unless Fusion GUI is connected to the device. To avoid such occurences in a running system, it is suggested to enable Packet Error Checking (PEC) in the PMBus host. The UCD90120A automatically detects and works with PMBus hosts, both with and without PEC enabled.

4. The fault log in UCD90120A is checksum protected. After new log entries are written into the fault log, the checksum is updated accordingly. After each device reset, UCD90120A re-calculates the fault log checksum and compares it with the existing checksum. If the two checksums are not the same, the device determines the fault log as corrupted and erases the fault log as a result.

In the event that the V33D power is dropped before the device finishes writing the fault log, the checksum will not be updated correctly, thus the fault log is erased at the next power-up. The results will be:

  • User sees an empty fault log
  • The device initialization time is approximately 160 ms longer than normal due to the Flash erasing time.

Such an event usually happens when the main power of the board drops and no standby power can stay alive for V33D. If such a scenario can be anticipated in an application, it is strongly suggested to use the brown-out function and circuit as described in the Brownout Function section.

5. Do not use RESET pin to power cycle the rails. Instead, use PMBus_CNTRL pin as described in the Power-Supply Sequencing section; or, use Pin-Selected Rail States function described in the Pin-Selected Rail States section.

6. When a pair of FPWM pin are configured as both Rail Enable and PWM(either margining or general purpose PWM) functions, there would be glitches on the pin configured as rail enable when device is out of reset and under initialization, which may impact the connected power rail. It is not recommended to have such configuration.

7. PMBus commands(system file, PMBus write script file) method is not recommended for the production programming because GPIO pins may have unexpected behaviors which can disable rails that provide power to device. Data flash hex file or data flash script file shall be used for production programming because GPIO pins are under controlled state.

8. It is mandatory that the V33D power shall be stable and no device reset shall be fired during the device programming. Data flash may be corrupted if failed to follow these rules.

9. When a pair of FPWM pins are both used for margining, after device is out of reset, the even FPWM pin may output some pulses which are up to the configured duty cycle and frequency. These pulses may cause unexpected behaviors on the margining rail if that rail is regulated before UCD is out of reset. It is recommended to use the even FPWM pin to margin rails that are directly controlled by the UCD90120A device.