JAJSDQ6 データシート

JAJSDQ6C June 2012 – September 2017

PRODUCTION DATA.

7 Detailed Description

7.1 Overview

The AFE4300 is a low-cost, integrated front-end designed for weight scales incorporating body-composition measurements. The AFE4300 integrates all the components typically used in a weight scale. The device has two signal chains: one for weight scale measurements and the other for body composition measurements. Both signal chains share a 16-bit, delta-sigma converter that operates at a data rate of up to 860 SPS. This device also integrates a reference and a low-dropout regulator (LDO) that generates a 1.7-V supply that can be used as the excitation source for the load cells, thus simplifying ratiometric measurements. Both the signal chains use a single digital-to-analog converter (DAC). The DAC is used to generate the dc signal for load-cell offset cancellation in the weight-scale chain. The same DAC is also used to generate the sine-wave modulation signal for the body-composition signal chain. Therefore, only one of the two signal chains can be activated at a time (using the appropriate register bits).

Two unique features of the AFE4300 are that the device provides an option for connecting up to four separate load cells, and supports tetrapolar measurements with I/Q measurements.

7.2 Functional Block Diagram

7.3 Feature Description

This section describes the details of the AFE4300 internal functional elements. The analog blocks are reviewed first, followed by the digital interface. The theory behind the body-composition measurement using the full-wave rectification method and the I/Q demodulation method are also described. The analog front-end is divided in two signal chains: a weight-measurement chain and a body-composition measurement front-end chain; both use the same 16-bit ADC and 6-bit DAC.

Throughout this document:

f_CLK denotes the frequency of the signal at the CLK pin.
t_CLK denotes the period of the signal at the CLK pin.
f_DR denotes the output data rate of the ADC.
t_DR denotes the time period of the output data.
f_MOD denotes the frequency at which the modulator samples the input.

7.3.1 Weight-Scale Analog Front-End

Figure 6 shows a top-level view of the front-end section devoted to weight-scale measurement. The weight-scale front-end has two stages of gain, with an offset correction DAC in the second gain stage. The first-stage gain is set by the external resistor and the second-stage gain is set by progamming the internal registers. For access and programming information, see the Register Maps section.

Figure 6. Weight-Scale Front-End

Though not shown in the diagram, an antialiasing network is required in front of the INA to filter out electromagnetic interference (EMI) signals or any other anticipated interference signals. A simple RC network is sufficient, combined with the attenuation provided by the on-chip decimation filter.

An internal reference source provides a constant voltage of 1.7 V at the VLDO output to drive the external bridge. The output of the bridge is connected to an INA (first stage). The first-stage gain (A₁) is set by the external resistor (R_G) and the 100-kΩ (±5%) internal feedback resistors (R_FB1) as shown in Equation 1:

Equation 1. AFE4300 EQ01_SBAS586.gif

The second-stage gain (A₂) is controlled by feedback resistors R_FB2, which have four possible values: 80 kΩ, 160 kΩ, 240 kΩ, and 320 kΩ. Because the gain is R_F / 80 kΩ, the gain setting can be 1, 2, 3, or 4. See the Register Maps section for details on setting the appropriate register bits.

7.3.1.1 Input Common Mode Range

The usable input common mode range of the weight-scale front-end depends on various parameters, including the maximum differential input signal, supply voltage, and gain. The output of the first-stage amplifier must be within 250 mV of the power supply rails for linear operation. The allowed common-mode range is determined by Equation 2:

Equation 2. AFE4300 EQ02_SBAS586.gif

where

V_{MAX_DIFF} = maximum differential input signal at the input of the first gain stage,
CM = Common-mode range.

For example, If AVDD = 2 V, the first stage gain = 183, and V_{MAX_DFF} = 7.5 mV (dc + signal), then:

1.06 V > CM > 0.936 V

7.3.1.2 Input Differential Dynamic Range

The max differential (INP – INN) signal depends on the analog supply, reference used in the system. This range is shown in Equation 3:

Equation 3. AFE4300 EQ03_SBAS586.gif

The gain in Equation 3 is the product of the gains of the INA and the second-stage gain. The full-scale input from the bridge signal typically consists of a differential dc offset from the load cell plus the actual weight signal. Having a high gain in the first stage helps minimize the effect of the noise addition from the subsequent stages. However, make sure to choose a gain that does not saturate the first stage with the full-scale signal. Also, the common-mode of the signal must fall within the range, as per Equation 2.

7.3.1.3 Offset Correction DAC

One way to increase the dynamic range of the signal chain is by calibrating the inherent offset of the load cell during the initial calibration cycle. The offset correction is implemented in the second stage with a 6-bit differential DAC, where each output is a mirror of the other and can source or sink up to 6.5 µA. The effect at the output of the second stage is an addition of up to ±6.5 µA × 2 × R_FB2. This effect is equivalent to a voltage at the input of the second stage (A+ / A–) of up to ±6.5 µA × 2 × 80 kΩ = ±1 V, when R_FB2 = 80 kΩ. The first-stage saturation cannot be avoided using this DAC. Because the offset correction DAC is a 6-bit DAC, the offset compensation step is 2 V / 2⁶ = 31.2 mV when referred to the input of the second stage.

7.3.1.3.1 Offset Correction Example

As an example, use a bridge powered from 1.7 V with 1.5 mV/V sensitivity and a potential offset between –4 mV and 4 mV. Worst case, the maximum signal is 4 mV of offset plus 1.7 × 1.5 mV/V = 2.55 mV of signal, for a total of 6.55 mV. The bridge common-mode voltage is ~0.85 V. The maximum excursion is 0.85 V – 0.25 V = 0.6 V (bottom rail) single-ended, on each output (A+ or A–). Therefore, ±1.2 V differentially at the output of the first stage prevents saturation. This result means that the first stage can have up to a gain of 1.2 V / 6.55 mV = 183.

Using this same example, the swing at the output of the first stage corresponding only to the potential offset range is 183 × ±4 mV = ±0.732 V. This swing can be completely removed at the output of the second stage by the offset correction (because the offset correction DAC has a ±1-V range) except for a maximum error of 31.2 mV.

7.3.2 Body Composition Measurement Analog Front-End

Body composition is traditionally obtained by measuring the impedance across several points on the body and matching the result in a table linking both the impedance measured and the body composition. This table is created by each manufacturer and is usually based on age group, sex, weight, and other parameters.

The body impedance that we want to measure, Z(f), is a function of the excitation frequency, and can be represented by polar or cartesian notations:

Equation 4. AFE4300 EQ04_SBAS586.gif

where

|Z| = sqrt(R² + X²)
θ = arctg(X/R)

The AFE4300 provides two options for body impedance measurement: ac rectification and I/Q demodulation. Both options work by injecting a sinusoidal current into the body and measuring the voltage across the body. The portion of the circuit injecting the current into the body is the same for each of those options. The difference, however, lies in how the measured voltage across the impedance is processed to obtain the final result.

7.3.2.1 AC Rectification

Figure 7 shows the portion of the AFE4300 devoted to body composition measurement in the RMS detector mode.

Figure 7. BCM in AC Rectifier Mode

The top portion of Figure 7 represents the current-injection circuit. A direct digital synthesizer (DDS) generates a sinusoidal digital pattern with a frequency obtained by dividing a 1-MHz clock with a 10-bit counter. The digital pattern drives a 6-bit, 1-MSPS DAC. The output of the DAC is filtered by a 150-kHz, second-order filter to remove the high-frequency images, followed by a series external capacitor to block the dc current and avoid any dc current injection into the body. The output of the filter (after the dc blocking capacitor) drives a resistor setting the amplitude of the current to be injected in the body, as shown in Equation 5:

Equation 5. AFE4300 EQ05_SBAS586.gif

The nominal DACOUT voltage (VDACOUT) is 1.05 V_PP (371.23 µVrms). The nominal value of R1 is 1.5 kΩ. So the nominal excitation current is 247.5 µArms. R1 can have a ±20% device-to-device variation, so the highest current is close to 300 µArms (850 µA_PP). The maximum voltage swing for the excitation electrodes (IOUT1-IOUT0) is 1 V_PP. This swing limits the recommended total impedance in feedback to approximately 1175 Ω. To reduce the excitation current, place an external resistor, R_DAC, (between DACOUT and DAC_FILT_IN) in series with R1. For example, with a 1.5-kΩ external resistor, the currents roughly reduce by 2X, thereby extending the range of the measured impedance.

Current flows into the body through an output analog multiplexer (mux) that allows the selection of up to six different contact points on the body. The same mux allows the connection of four external impedances for calibration. The current crosses the body impedance and a second mux selects the return path (contact) on the body, closing the loop to the output of the amplifier.

At the same time that the current is injected, a second set of multiplexers connects a differential amplifier across the same body impedance in order to measure the voltage drop created by the injected current, shown by Equation 6:

Equation 6. AFE4300 EQ06_SBAS586.gif

where

The output of the amplifier is routed to a pair of switches that implement the demodulation at the same frequency as the excitation current source in order to drive the control of those switches. This circuit performs a full-wave rectification of the differential amplifier output and a low-pass filter at the output, recovers the dc level, and finally routes the amplifier output to the same 16-bit digitizer used in the weight-scale chain.

Equation 7. AFE4300 EQ07_SBAS586.gif

Ultimately, the dc output is proportional to the module of the impedance. The proportionality factor can be obtained through calibration with the four external impedances. Although, with one single frequency or measurement, only the module of the impedance can be obtained; two different frequencies could be used to obtain both the real and the imaginary parts.

7.3.2.2 I/Q Demodulation

The AFE4300 includes a second circuit that with a single frequency measurement, obtains both the real and the imaginary portions, as shown in Figure 8. As explained previously, the portion of the circuit injecting the current into the body is the same for both configurations. Therefore, the circuit is the same in Figure 7 and Figure 8. The difference between them is that an I/Q demodulator is used in this second approach, as shown in Figure 8.

Figure 8. BCM in I/Q Demodulator Mode

As with the case of the RMS detector, a differential amplifier measures the voltage drop across the impedance, as shown in Equation 8:

Equation 8. AFE4300 EQ08_SBAS586.gif

where

Z = the module of the impedance at ω₀
θ = phase of the impedance at ω₀

The I/Q demodulator takes the v(t) signal and outputs two dc values. These two values are used to extract the impedance module and phase with a single frequency measurement. Figure 8 shows the block diagrm of the implementation. Using the I/Q demodulator helps reduce power consumption and still yields excellent performance. The local oscillator (LO) signals for the mixers are generated from the same clock driving the DDS/DAC and are of the same phase and frequency as the sinusoidal i(t) (see Equation 5). The LO signals directly control the switches on the in-phase (I) path, and after a delay of 90° degrees, control the switches on the quadrature (Q) path. This switching results in multiplying the v(t) signal by a square signal swinging from –1 to 1.

Breaking down the LO signal into Fourier terms results in Equation 9:

Equation 9. AFE4300 EQ09_SBAS586.gif

Therefore, the output voltage of the mixer is as shown in Equation 10:

Equation 10. AFE4300 EQ10_SBAS586.gif

where

Applying fundamental trigonometry gives Equation 11:

Equation 11. AFE4300 EQ11_SBAS586.gif

Each product of sinusoids can be broken up in an addition of two sinusoids. Equation 12 shows the first term:

Equation 12. AFE4300 EQ12_SBAS586.gif

Equation 13 shows the 2nd product:

Equation 13. AFE4300 EQ13_SBAS586.gif

And so on. Performing the same analysis on the Q side, the output voltage of the mixer is shown in Equation 14:

Equation 14. AFE4300 EQ14_SBAS586.gif

Agiain, applying fundamental trigonometry gives Equation 15:

Equation 15. AFE4300 EQ15_SBAS586.gif

Each of the products can be broken up into sums. Starting with the first product, as shown in Equation 16:

Equation 16. AFE4300 EQ16_SBAS586.gif

And so on. Note that on I(t) as well as on Q(t), all the terms beyond the cutoff frequency of the low-pass filter at the output of the mixers (setup by the two 1-kΩ resistors and an external capacitor) are removed, leaving only the dc terms, giving Equation 17 for I_DC and Equation 18 for Q_DC:

Equation 17. AFE4300 EQ17_SBAS586.gif

Equation 18. AFE4300 EQ18_SBAS586.gif

In reality, the LO amplitude is not known (likely, not ±1) and affects the value of K in Equation 17 and Equation 18. Solving these two equations gives Equation 19:

Equation 19. AFE4300 EQ19_SBAS586.gif

In order to account for all the nonidealities in the system, the AFE4300 also offers four extra terminals on the driving side (two to drive, and two for the currents to return) and four extra terminals on the receive/differential-amplifier side. As with RMS mode, these spare terminals allow for connection of up to four external calibration impedances, and they also compute K.

7.3.3 Digitizer

The digitizer block includes an analog mux and a 16-bit sigma-delta ADC.

7.3.3.1 Multiplexer

There are two levels of analog mux. The first level selects from among the outputs of the weight scale, the body composition function, two auxiliary inputs, and the battery monitor. A second mux is used to obtain the measurement of the outputs coming from the first mux, either differentially or with respect to ground (single-ended). Note that when measuring single-ended inputs, the negative range of the output codes are not used. For battery or AVDD monitoring, an internal 1/3 resistor divider is included that enables the measurement using only one reference setting for any battery voltage, thus simplifying the monitoring routine.

7.3.3.2 Analog-to-Digital Converter

The 16-bit, delta-sigma, ADC operates at a modulator frequency of 250 kHz with an f_CLK of 1 MHz. The full-scale voltage of the ADC is set by the voltage at the reference (V_REF). The reference can be either the LDO output (1.7 V) for the weight-scale front-end or the internally-generated reference signal (1.7 V) for the BCM front-end.

The decimation filter at the output of the modulator is a single-order sinc filter. The decimation rate can be programmed to provide data rates from 8 SPS to 860 SPS with an f_CLK of 1 MHz. Refer to the ADC_CONTROL_REGISTER1 register in the Register Maps section for details on programming the data rates. Figure 9 shows the frequency response of the digital filter for a data rate of 8 SPS. Note that the modulator has pass band around integer multiples of the modulator sampling frequency of 250 kSPS. Set the corner frequency of the antialiasing network before the INA so that there is adequate attenuation at the first multiple of the modulator frequency.

Figure 9. Frequency Response

The output format of the ADC is twos complement binary. Table 1 describes the output code versus the input signal, where full-scale (FS) is equal to the V_REF value.

Table 1. Input Signal Versus Ideal Output Code

INPUT SIGNAL, V_IN (AIN_P – AIN_N)	IDEAL OUTPUT CODE
≥ FS (2¹⁵ – 1)/2¹⁵	7FFFh
+FS/2¹⁵	0001h
0	0
–FS/2¹⁵	FFFFh
≤ –FS	8000h

7.3.4 Reset and Power-Up

After power up, the device needs to be reset to get all the internal registers to their default state. Resetting the device is done by applying a zero pulse in the RST line for more than 20 ns after the power is stable for 5 ms. After 30 ns, the first access can be initiated (first falling edge of STE). As part of the reset process, the AFE4300 sets all of the register bits to the respective default settings. Some of the register bits must be written after reset and power up for proper operation. Refer to the Register Maps section for more details. By default, the AFE4300 enters into a power-down state at start-up. The device interface and digital are active, but no conversion occurs until the ADC_PD bit is written to. The initial power-down state of the AFE4300 is intended to relieve systems with tight power-supply requirements from encountering a surge during power-up.

7.3.5 Duty Cycling for Low Power

For many applications, improved performance at low data rates may not be required. For these applications, the AFE4300 supports duty cycling that can yield significant power savings by periodically requesting high data-rate readings at an effectively lower data rate. For example, an AFE4300 in power-down mode with a data rate set to 860 SPS could be operated by a microcontroller that instructs a single-shot conversion every 125 ms (8 SPS). Because a conversion at 860 SPS only requires approximately 1.2 ms, the AFE4300 automatically enters power-down mode for the remaining 123.8 ms. In this configuration, the digitizer consumes about 1/100th the power of the digitizer when operated in Continuous-Conversion mode. The rate of duty cycling is completely arbitrary and is defined by the master controller.

7.4 Device Functional Modes

7.4.1 Operating Modes

The ADC operates in one of two conversion modes: Continuous-Conversion or Single-Shot conversion. The conversion mode is set using the ADC_CONV_MODE bit. In Continuous-Conversion mode, the ADC continuously performs conversions when the ADC_PD bit is set to 0. When a conversion completes, the ADC places the result in a register, issues an interrupt on the RDY pin, and immediately begins another conversion. In this mode, if ADC_PD is set to 1, then the ADC goes into a power-down state.

To get a Single-Shot conversion, the ADC_PD bit is to be first set to 1. When the ADC_CONV_MODE is subsequently set to 1, then the Single-Shot conversion is enabled. When enabled, the ADC does a single conversion and gives an interrupt on the RDY pin. To do one more Single-Shot conversion, the ADC_CONV_MODE bit must be set to 0 and then 1 again (with the ADC_PD bit at 1).

7.5 Programming

7.5.1 Serial Interface

The SPI™-compatible serial interface consists of either four signals (STE, SCLK, SDIN, and SDOUT) or three signals (in which case, STE can be tied low). The interface is used to read conversion data, read from and write to registers, and control AFE4300 operation. The data packet (between falling and rising edge of STE) is 24 bits long and is serially shifted into SDIN with the MSB first. The first eight bits (MSB) represent the address of the register being accessed and last 16 bits (LSB) represent the data to be stored or read from that address. For the eight bits address, the lower five bits [20:16] are the real address bits. Bit 21 is the read and write bit.

'0' in bit 21 defines a write operation of the 16 data bits [15:0] into the register defined by the address bits [20:16].
'1' in bit 21 triggers a read operation of the register defined by the address bits [20:16]. The data are output into SDOUT with every rising edge of SCLK, starting at the ninth rising edge. At the same time, data in SDIN are shifted inside the 16 data bits of that given register. Note that every time a register is read, the register must be rewritten except when reading the data output register.

7.5.1.1 SPI Enable (STE)

The STE pin selects the AFE4300 for SPI communication. This feature is useful when multiple devices share the serial bus. STE must remain low for the duration of the serial communication. When STE is taken high, the serial interface is reset, and SCLK is ignored.

7.5.1.2 Serial Clock (SCLK)

The SCLK pin features a Schmitt-triggered input and is used to clock data on the DIN and RDY pins into and out of the AFE4300. Even though the input has hysteresis, SCLK is recommended to be kept as clean as possible to prevent glitches from accidentally shifting the data. When the serial interface is idle, hold SCLK low.

7.5.1.3 Data Input (SDIN)

The data input pin (SDIN) is used along with SCLK to send data to the AFE4300 (opcode commands and register data). The device latches data on SDIN on the falling edge of SCLK. The AFE4300 never drives the SDIN pin. Note that every time a register is read, the register must be rewritten, except when reading the data output register.

7.5.1.4 Data Output (SDOUT)

The data output and data ready pin (RDY) are used with SCLK to read conversion and register data from the AFE4300. In Read Data Continuous mode, RDY goes low when conversion data are ready, and goes high 8 μs before the data ready signal. Data on RDY are shifted out on the rising edge of SCLK. If the AFE4300 does not share the serial bus with another device, STE may be tied low. Note that every time a register is read, the register must be rewritten, except when reading the data output register.

7.5.1.5 Data Ready (RDY)

RDY acts as a conversion ready pin in both Continous-Conversion mode and Single-Shot mode. When in Continuous-Conversion mode, the AFE4300 provides a brief (~8 μs) pulse on the RDY pin at the end of each conversion. In Single-Shot mode, the RDY pin asserts low at the end of a conversion. Figure 10 and Figure 11 show the timing diagram for these two modes.

Figure 10. Timing for Single-Shot Mode

Figure 11. Timing for Continuous Mode

7.6 Register Maps

7.6.1 Register Map

Table 2 describes the registers of the AFE4300.

Table 2. Register Map

REGISTER NAME	CONTROL	ADDRESS	DESCRIPTION	DEFAULT
DEVICE CONTROLS
DEVICE_CONTROL1	(See Description)	0x09[14:13]	Write '11' after power up and/or reset	00b
	DAC_PD	0x09[3]	Enable DAC for WS, BC measurements	0b
	PDB	0x09[2]	Chip power down	0b
	BCM_PDB	0x09[1]	Body composition measurement front-end power down	0b
	WS_PDB	0x09[0]	Weight-scale front-end power down	0b
DEVICE_CONTROL2	BAT_MON_EN1	0x0F[7]	Enables battery monitoring along with bit[0]	0b
DEVICE_CONTROL2	BAT_MON_EN2	0x0F[0]	Enables battery monitoring along with bit[7]	0b
ADC CONTROLS
ADC_DATA_RESULT	(See Description)	0x00[15:0]	ADC data result, read only register
ADC_CONTROL_REGISTER1	ADC_CONV_MODE	0x01[15]	Continuous-Conversion or Single-Shot mode	0b
	ADC_MEAS_MODE	0x01[13:11]	Single-Ended or Differential mode	000b
	ADC_PD	0x01[7]	ADC power down	1b
	ADC_DATA_RATE	0x01[6:4]	ADC data-rate control bits	100b
ADC_CONTROL_REGISTER2	ADC_REF_SEL	0x10[6:5]	Reference selection bits	00b
ADC_CONTROL_REGISTER2	PERIPHERAL_SEL	0x10[4:0]	Peripheral selection bits	00000b
WEIGHT-SCALE MODES
DEVICE_CONTROL2	BRIDGE_SEL	0x0F[2:1]	Selects one of the four bridge inputs	00b
WEIGHT_SCALE_CONTROL	WS_PGA_GAIN	0x0D[14:13]	PGA gain of weight-scale front-end	00b
WEIGHT_SCALE_CONTROL	OFFSET_DAC_VALUE	0x0D[5:0]	Offset DAC setting for weight-scale front-end	000000b
BCM CONTROLS
ISW_MUX	ISW_MUXP	0x0A[15:8]	Control for switches IOUTP and RP	0x00
ISW_MUX	ISW_MUXM	0x0A[7:0]	Control for switches IOUTN and RN	0x00
VSENSE_MUX	VSENSE_MUXP	0x0B[15:8]	Control for switches VSENSEP and VSENSEP_R	0x00
VSENSE_MUX	VSENSE_MUXM	0x0B[7:0]	Control for switches VSENSEN and VSENSN_R	0x00
BCM_DAC_FREQ	DAC_FREQ	0x0E[9:0]	Sets the frequency of BCM excitation current source	0x00
IQ_MODE_ENABLE	IQ_MODE_ENABLE	0x0C[11]	Enable IQ demodulator	0b
DEVICE_CONTROL2	IQ_DEMOD_CLK_DIV_FAC	0x0F[13:11]	IQ Demodulator clock frequency	000b
MISCELLANEOUS REGISTERS
MISC_REGISTER1	(See Description)	0x02[15:0]	Write 0x0000 after power up and/or reset	0x8000
MISC_REGISTER2	(See Description)	0x03[15:0]	Write 0xFFFF after power up and/or reset	0x7FFF
MISC_REGISTER3	(See Description)	0x1A[15:0]	Write 0x0030 after power up and/or reset	0x0000

7.6.1.1 ADC_DATA_RESULT (Address 0x00, Default 0x0000)

This register stores the most recent conversion data in twos complement format with the MSB in bit 15 and the LSB in bit 0.

7.6.1.2 ADC_CONTROL_REGISTER1 (Address 0x01, Default 0x01C3)

This register is used in conjunction with ADC_PD (bit 7). Refer to the description of the ADC_PD bit for more details.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
ADC_CONV_MODE	1	ADC_MEAS_MODE			0	0	1	ADC_ PD	ADC_DATA _RATE			0	0	0	0

Bit 15	ADC_CONV_MODE: ADC conversion mode/ADC single-shot conversion start.
	This bit determines the operational status of the device. This bit can only be written when in the ADC power-down mode. When read, this bit gives the status report of the conversion.
	For a write status: 0 : No effect (default) 1 : Single-shot conversion mode
	For a read status: 0 : Device currently performing a conversion 1 : Device not currently performing a conversion
Bit 14	Always write ‘1’.
Bits[13:11]	ADC_MEAS_MODE: ADC measurement mode selection.
	These bits set the ADC measurements to be either single-ended or differential.

	ADC_MEAS_MODE	ADC AINP, AINM
	000 (default) 001 010	A1, A2 = differential (default) A1, AVSS = single-ended A2, AVSS = single-ended

Bits[10:8]	Always write '001'
Bit 7	ADC_PD: ADC Powerdown
	This bit powers down the ADC_PGA and the ADC. By default, the ADC is powered down (ADC_PDN = '1'). For continuous conversion mode, this bit must to set to '0'. For single-shot mode, this bit must be set to ‘1’ along with bit 15. During single-shot conversion mode, the device automatically powers up the ADC, triggers one ADC conversion, and then powers down the ADC.

	ADC_CONV_MODE (Bit 15)	ADC_PDN (Bit 7)	MODE
	X 0 1	0 1 (default) 1 (default)	Continuous conversion ADC PD Single-shot

Bits[6:4]	ADC_DATA_RATE: Conversion rate select bits.
	These bits select one of eight different ADC conversion rates. The data rates shown assume a master clock of 1 MHz.
	000: 8 SPS 001: 16 SPS 010: 32 SPS 011: 64 SPS 100: 128 SPS (default) 101: 250 SPS 110: 475 SPS 111: 860 SPS
Bits[3:0]	Always write '0000'. At power up, these bits are set as '0011'.

7.6.1.3 MISC_REGISTER1 (Address 0x02, Default 0x8000)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

Bit 15	Always write ‘0’. At power up, this bit is set as '1'.
Bits[14:0]	Not used, always write ‘0’. At power up, these bits are set as '0'.

7.6.1.4 MISC_REGISTER2 (Address 0x03, Default 0x7FFF)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	1	1	1	1	1	1	1	1	1	1	1	1	1	1	1

Bit 15	Always write ‘1’. At power up, this bit is set as '0'.
Bits[14:0]	Always write ‘1’. At power up, these bits are set as '1'.

7.6.1.5 DEVICE_CONTROL1 (Address 0x09, Default 0x0000)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	1	1	0	0	0	0	0	0	0	0	0	DAC_PD	PDB	BCM_PDB	WS_ PDB

Bits[15]	Not used. Always write '0'.
Bits[14:13]	Not used. Always write '1'.
Bits[12:4]	Not used. Always write '0'.
Bit 3	DAC_PDB: Power down DAC.
	This bit powers down the weight-scale front-end offset correction DAC and the BCM front-end current source DAC.
	0: Power up DAC (default) 1: Power down DAC
Bit 2	PDB: Power down device.
	This bit in conjunction with the other power-down bits determines the power state of the device.
	0: Power down (default) 1: Power up of front-end
Bit 1	BCM_PDB: Body composition measurement front-end power-down bit.
	0: Power down body compositionmeasurement front-end (default) 1: Power up body composition measurement front-end. Power down the weight scale when powering up the BCM.
Bit 0	WS_PDB: Weight-scale front-end power-down bit.
	0: Power down weight-scale front-end (default) 1: Power up weight-scale front-end. Power down BCM when powering up the weight scale.

Table 3 shows the available power-down modes.

Table 3. Power-Down Modes

DAC_PDB (Bit3)	PDB (Bit 2)	BCM_PDB (Bit 1)	WS_PDB (Bit 0)	ADC_PD (Bit 7, ADC Control Register)	MODE
X	0	0	0	1	Full device power down
1	1	0	0	1	Sleep mode
0	1	1	0	0	Weight-scale power down, body composition measurement
0	1	0	1	0	Body composition measurement power down, weight-scale measurement
0	1	0	0	0	Weight-scale and body composition measurement power down (aux/battery measurement)

7.6.1.6 ISW_MUX (Address 0x0A, Default 0x0000)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
IOUTP5	IOUTP4	IOUTP3	IOUTP2	IOUTP1	IOUTP0	RP1	RP0	IOUTN5	IOUTN4	IOUTN3	IOUTN2	IOUTN1	IOUTN0	RN1	RN0

Bits[15:10]	IOUTP[5:0]
	These bits close the switches routing IOUTPx to the output of OPAMP1.
	0: Switch is open (default) 1: Switch is closed
Bits[9:8]	RP[1:0]
	These bits close the switches routing the calibration signal to the output of OPAMP1.
	0: Switch is open (default) 1: Switch is closed
Bits[7:2]	IOUTN[5:0]
	These bits close the switches routing IOUTNx to the negative input of OPAMP1.
	0: Switch is open (default) 1: Switch is closed
Bits[1:0]	RN[1:0]
	These bits close the switches routing the calibration signal to the negative input of OPAMP1.
	0: Switch is open (default) 1: Switch is closed

7.6.1.7 VSENSE_MUX (Address 0x0B, Default 0x0000)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
VSENSEP5	VSENSEP4	VSENSEP3	VSENSEP2	VSENSEP1	VSENSEP0	VSENSEP_R1	VSENSEP_R0	VSENSEN5	VSENSEN4	VSENSEN3	VSENSEN2	VSENSEN1	VSENSEN0	VSENSEM_R1	VSENSEM_R0

Bits[15:10]	VSENSEPx[5:0]
	These bits close the switches routing VSENSEPx to the positive input of the receive amplifier.
	0: Switch is open (default) 1: Switch is closed
Bits[9:8]	VSENSEP_Rx[1:0]
	These bits close the switches routing the calibration signal to the positive input of the receive amplifier.
	0: Switch is open (default) 1: Switch is closed
Bits[7:2]	VSENSENx[5:0]
	These bits close the switches routing VSENSENx to the negative input of the receive amplifier.
	0: Switch is open (default) 1: Switch is closed
Bits[1:0]	VSENSEM_Rx[1:0]
	These bits close the switches routing the calibration signal to the negative input of the receive amplifier.
	0: Switch is open (default) 1: Switch is closed

7.6.1.8 IQ_MODE_ENABLE (Address 0x0C, Default 0x0000)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	IQ_MODE_ ENABLE	0	0	0	0	0	0	0	0	0	0	0

Bits[15:12]	Not used. Always write '0'.
Bit 11	IQ_MODE_ENABLE: Enable the I/Q demodulator.
	This bit sets the impedece measurement mode to either full-wave rectifier mode or I/Q demodulator mode. For I/Q Demodulator mode, the DAC_FREQ bits of the BCM_DAC_FREQ register and the IQ_DEMOD_CLK_DIV_FAC bits of the DEVICE_CONTROL2 register must be set appropriately. Refer to the respective register section for more details.
	0: Full-Wave Rectifier mode (default) 1: I/Q Demodulator mode
Bits[10:0]	Not used. Always write '0'.

7.6.1.9 WEIGHT_SCALE_CONTROL (Address 0x0D, Default 0x0000)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	WS_PGA_ GAIN		0	0	0	0	0	0	0	OFFSET_DAC_VALUE

Bit 15	Not used. Always write '0'.
Bits[14:13]	WS_PGA_GAIN: Sets the second-stage gain of the weight-scale front-end.
	00: Gain = 1 (default) 01: Gain = 2 10: Gain = 3 11: Gain = 4
Bits[12:6]	Not used. Always write '0'.
Bit[5:0]	OFFSET_DAC_VALUE: Offset correction DAC setting.
	These bits set the value for the DAC used to correct the input offset of the weight-scale front-end. The correction is made at the second stage. The offset correction at the output of the first stage is given by OFFSET_DAC_VALUE × 31.2 mV. Note that OFFSET_DAC_VALUE is a number from –32 to 31, in twos complement; default is '000000'.

7.6.1.10 BCM_DAC_FREQ (Address 0x0E, Default 0x0000)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	0	DAC9	DAC8	DAC7	DAC6	DAC5	DAC4	DAC3	DAC2	DAC1	DAC0

Bits[15:910]	Not used. Always write '0'.
Bits[9:0]	DAC[9:0]: Sets the frequency of the BCM excitation current source.
	The DAC output frequency is given by DAC[9:0] × f_CLK / 1024, where f_CLK is the frequency of the device input clock (pin 79). All combinations of the DAC frequency can be used for the full-wave rectifier mode. However, only certain combinations of the DAC frequency can be used for the IQ demodulator mode. Refer to the description of the DEVICE_CONTROL2 register for more details.
	For example, with f_CLK = 1.024 MHz: DAC = 0x00FF → 255 kHz DAC = 0x0001 → 1 kHz

7.6.1.11 DEVICE_CONTROL2 (Address 0x0F, Default 0x0000)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	IQ_DEMOD_CLK_ DIV_FAC			0	0	0	BAT_MON_EN1	0	0	0	0	BRIDGE_SEL		BAT_MON_EN0

Bits[15:14]	Not used. Always write '0'.
Bits[13:11]	IQ_DEMOD_CLK_DIV_FAC: I/Q demodulator clock frequency.
	The clock for the IQ demodulator (IQ_DEMOD_CLK signal) is internally generated from the device input clock (f_CLK) by a divider controlled by this register. Note that the IQ_DEMOD_CLK must be four times the BCM_DAC_FREQ so that the phases for the mixers can be generated (that is, IQ_DEMOD_CLK = f_CLK / (IQ_DEMOD_CLK_DIV_FAC) = BCM_DAC_FREQ × 4)
	000: Divide by 1 (default) 001: Divide by 2 010: Divide by 4 011: Divide by 8 100: Divide by 16 Others: Divide by 32
Bit 7	BAT_MON_EN1: This bit (along with BAT_MON_EN0, bit 0) enables battery monitoring.
	When disabled, the battery monitoring block is powered down to save power. See the description of BAT_MON_EN0, bit 0.
Bits[6:3]	Not used. Always write '0'.
Bits[2:1]	BRIDGE_SEL: Selects one of the four input pairs to be routed to the weight-scale front-end.
	00: Bridge 1 (INP1, INM1) connected to the weight-scale front-end (default) 01: Bridge 2 (INP2, INM2) connected to the weight-scale front-end 10: Bridge 3 (INP3, INM3) connected to the weight-scale front-end 11: Bridge 4 (INP4, INM4) connected to the weight-scale front-end.
Bit 0	BAT_MON_EN0: This bit along with BAT_MON_EN1 (Bit[7]) enables battery monitoring.
	00: Monitor disabled (default) 11: Monitor enabled (AVDD / 3)
	NOTE: The PERIPHERAL_SEL bits of the ADC_CONTROL_REGISTER2 must be set to '10001' in order to route the battey monitor output to the ADC.

7.6.1.12 ADC_CONTROL_REGISTER2 (Address 0x10, Default 0x0000)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	0	0	ADC_REF_SEL		PERIPHERAL_SEL

Bits[15:7]	Not used. Always write '0'.
Bits[6:5]	ADC_REF_SEL[1:0]: Selects the reference for the ADC.
	00: ADCREF connected to VLDO. Used for ratiometric weight-scale measurement (default). 01, 10: Do not use 11: ADCREF connected to VREF (internal voltage reference generator). Used for impedance measurement.
Bits[4:0]	PERIPHERAL_SEL[4:0]: Selects the signals that are connected to the ADC.
	00000: Output of the weight-scale front-end (default) 00011: Output of the body composition measurement front-end (OUTP_FILT/OUTM_FILT) 00101: Output of the body composition measurement front-end (OUTP_Q_FILT/OUTM_Q_FILT) 01001: AUX1 signal for single-ended measurement. Also set bit[13:11] of the ADC_CONTROL_REGISTER1 to '001'. 10001: AUX2 signal for single-ended measurement. Also set bit[13:11] of the ADC_CONTROL_REGISTER1 to '010'. 11001: AUX2 and AUX1 signal for differential measurement (AUX2-AUX1). Also set bit[13:11] of the ADC_CONTROL_REGISTER1 to 000.
	NOTE: All other bit combinations are invalid.

7.6.1.13 MISC_REGISTER3 (Address 0x1A, Default 0x0000)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
0	0	0	0	0	0	0	0	0	0	1	1	0	0	0	0

Bits[15:6]	Not used. Always write '0'.
Bits[5:4]	Always write '1'.
Bits[3:0]	Not used. Always write '0'.