JAJSEF2D June   2013  – December 2021 DAC7760 , DAC8760

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: AC
    7. 7.7  Timing Requirements: Write Mode
    8. 7.8  Timing Requirements: Readback Mode
    9. 7.9  Timing Diagrams
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  DAC Architecture
      2. 8.3.2  Voltage Output Stage
      3. 8.3.3  Current Output Stage
      4. 8.3.4  Internal Reference
      5. 8.3.5  Digital Power Supply
      6. 8.3.6  DAC Clear
      7. 8.3.7  Power-On Reset
      8. 8.3.8  Alarm Detection
      9. 8.3.9  Watchdog Timer
      10. 8.3.10 Frame Error Checking
      11. 8.3.11 User Calibration
      12. 8.3.12 Programmable Slew Rate
    4. 8.4 Device Functional Modes
      1. 8.4.1 Setting Voltage and Current Output Ranges
      2. 8.4.2 Boost Configuration for IOUT
      3. 8.4.3 Filtering the Current Output (only on the VQFN package)
      4. 8.4.4 HART Interface
        1. 8.4.4.1 For 4-mA to 20-mA Mode
        2. 8.4.4.2 For All Current Output Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
        1. 8.5.1.1 SPI Shift Register
        2. 8.5.1.2 Write Operation
        3. 8.5.1.3 Read Operation
        4. 8.5.1.4 Stand-Alone Operation
        5. 8.5.1.5 Multiple Devices on the Bus
    6. 8.6 Register Maps
      1. 8.6.1 DACx760 Command and Register Map
        1. 8.6.1.1 DACx760 Register Descriptions
          1. 8.6.1.1.1 Control Register
          2. 8.6.1.1.2 Configuration Register
          3. 8.6.1.1.3 DAC Registers
          4. 8.6.1.1.4 Reset Register
          5. 8.6.1.1.5 Status Register
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Controlling the VOUT and IOUT Pins
        1. 9.1.1.1 VOUT and IOUT Pins are Independent Outputs, Never Simultaneously Enabled
        2. 9.1.1.2 VOUT and IOUT Pins are Independent Outputs, Simultaneously Enabled
        3. 9.1.1.3 VOUT and IOUT Pins are Tied Together, Never Simultaneously Enabled
      2. 9.1.2 Implementing HART in All Current Output Modes
        1. 9.1.2.1 Using CAP2 Pin on VQFN Package
        2. 9.1.2.2 Using the ISET-R Pin
      3. 9.1.3 Short-Circuit Current Limiting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Typical Characteristics

at TA = 25°C (unless otherwise noted)

GUID-1BBE4D57-1ADB-476D-AED0-6247C71BB601-low.png
 
Figure 7-3 REFOUT vs Temperature
GUID-C4A0CB9F-9A4D-495E-BCF6-DFE0785BF889-low.png
 
Figure 7-5 REFOUT vs Load Current
GUID-B10BFA8E-F393-49CA-8C20-EEB2E63ADDB7-low.png
 
Figure 7-7 REFOUT Noise PSD vs Frequency
GUID-B72245D0-5721-46CA-97A3-6AB82FAE1074-low.png
 
Figure 7-9 REFOUT Transient vs Time
GUID-C50835F8-7227-43A0-B9CB-C5E9B55F7437-low.png
 
Figure 7-11 AIDD vs AVDD
GUID-5A421E5F-65EE-41F9-8D7E-749914BA0326-low.png
 
Figure 7-13 Internal DVDD vs Load Current
GUID-F1E8FC8F-5587-410C-B2A5-D07A59813A6E-low.png
 
Figure 7-15 VOUT TUE vs Code (Unipolar Outputs)
GUID-E0AF877F-7B28-46AC-8F20-D7116EF88AB2-low.png
 
Figure 7-17 VOUT TUE vs Temperature
GUID-886C0C03-4309-4466-A2B3-6F1810A362F6-low.png
 
Figure 7-19 VOUT INL vs Code (Unipolar Outputs)
GUID-5026E53F-8298-4408-AC2D-4BAD51D9F503-low.png
 
Figure 7-21 VOUT INL vs Temperature
GUID-BE623A5F-1A4E-45A8-84B7-82AAF7294927-low.png
 
Figure 7-23 VOUT DNL vs Code (Unipolar Outputs)
GUID-3997314E-94CD-4696-8C06-9FF3E4AC3C92-low.png
 
Figure 7-25 VOUT DNL vs Temperature
GUID-F8C2FD55-558D-4733-BCE6-CAE67F553FC4-low.png
 
Figure 7-27 VOUT Full-Scale Error vs Temperature
GUID-55ACDCC7-0871-4565-BE98-E2C25C5CF2F4-low.png
 
Figure 7-29 Bipolar Zero Error vs Temperature
GUID-2E8658B9-7AFB-4236-8146-4C370DBA364E-low.png
 
Figure 7-31 Zero-Scale Error vs Temperature
GUID-88F59EA8-D9EF-44DF-B4EF-5DAA4C169B58-low.png
 
Figure 7-33 VOUT (Zero-Scale) vs Load Current
(Source or Sink)
GUID-7733DC25-1195-4A32-A2AD-A3739D68F6F1-low.png
 
Figure 7-35 BP10V Falling
GUID-4C655953-4B91-44AE-9854-F59D685E3DD0-low.png
 
Figure 7-37 VOUT Settling Time vs LOAD
(100 pF Between VOUT and CMP Pins)
GUID-083D7F28-C0F0-4D37-9370-2D5CA2B44943-low.png
 
Figure 7-39 VOUT Power-On Glitch
GUID-916C8F33-CABA-4E08-AFF8-288794B9AE7A-low.png
 
Figure 7-41 VOUT Noise PSD vs Frequency
GUID-771FBE90-D0F9-4758-8839-500C3E3F90A1-low.png
 
Figure 7-43 VOUT Hi-Z Leakage Current vs Voltage
GUID-00D6F947-F5C4-4E54-96E4-A9E5B47246E5-low.png
 
Figure 7-45 AVDD PSRR for VOUT
GUID-2A15BB79-D0AC-4BEF-BA34-C3A21CBD30F8-low.png
 
Figure 7-47 IOUT TUE vs Code (0 mA to 20 mA)
GUID-C94FAA85-4D5F-487E-916F-C79B731A693E-low.png
 
Figure 7-49 IOUT TUE vs Temperature (Internal RSET)
GUID-8AD1F619-61BF-48D8-B866-A9AE6D5A2C53-low.png
 
Figure 7-51 IOUT TUE vs Supply (Internal RSET)
GUID-CD037D15-8B00-466A-A56F-E907D46C278C-low.png
 
Figure 7-53 IOUT INL vs Code (0 mA to 24 mA)
GUID-BD7AE722-21FD-46F7-B345-CB52ACDF7759-low.png
 
Figure 7-55 IOUT INL vs Code (4 mA to 20 mA)
GUID-48EB1BAC-BB1A-494B-99D6-5738CB3D337A-low.png
 
Figure 7-57 IOUT INL vs Temperature (External RSET)
GUID-4C5C3DEF-690E-4057-B74F-B78BEBF368BC-low.png
 
Figure 7-59 IOUT INL vs Supply (External RSET)
GUID-4F1DA93B-C373-4633-AA5D-84DA93A11B0F-low.png
 
Figure 7-61 IOUT DNL vs Code (0 mA to 20 mA)
GUID-EC7F1A28-EFB9-433E-ACC2-29AC2BDFC359-low.png
 
Figure 7-63 IOUT DNL vs Temperature (Internal RSET)
GUID-12213E29-EE3F-4642-B22D-6078C9DDAEA8-low.png
 
Figure 7-65 IOUT DNL vs Supply (Internal RSET)
GUID-C1960739-F33A-4130-85E5-FE806D97D17B-low.png
 
Figure 7-67 IOUT Full-Scale Error vs Temperature
GUID-B4EA2CBE-5462-4F0A-96E2-AB167725310F-low.png
 
 
Figure 7-69 IOUT Gain Error vs Temperature
GUID-68910F71-B8D6-4CE8-810F-24AE6229D191-low.png
Compliance voltage headroom is defined as the drop from AVDD pin to the IOUT pin.
Figure 7-71 IOUT vs Compliance Headroom Voltage
GUID-72D556D2-553E-4A3C-BC0D-582BE2F38BBE-low.png
 
Figure 7-73 4-mA to 20-mA Falling
GUID-589E21B7-02FC-4AAA-B2AF-144C322FF88D-low.png
 
Figure 7-75 IOUT Output Enable Glitch
GUID-DFF49AEC-0AC4-4E78-9DB1-ECECDDC5904D-low.png
 
Figure 7-77 IOUT Noise PSD vs Frequency
GUID-C3E8E34D-C5CF-41B5-95D5-9737A4290A9F-low.png
 
Figure 7-79 IOUT Hi-Z Leakage Current vs Voltage
GUID-D009A858-C840-406B-8156-D936F9D63867-low.png
 
Figure 7-4 Internal Reference Temperature Drift Histogram
GUID-6DED1EB5-2BF4-413A-95E9-CFA2EA729CE7-low.png
 
Figure 7-6 REFOUT vs AVDD
GUID-FF01FB57-C84C-49AB-9CE9-BAAFD70EFE95-low.png
 
Figure 7-8 Internal Reference, Peak-to-Peak Noise
(0.1 Hz to 10 Hz)
GUID-12C11EF9-B963-4709-80A7-3E4F89A515FC-low.png
 
Figure 7-10 AIDD or AISS vs AVDD or AVSS
GUID-7AC56F7E-A7C3-4B76-BE91-E532CA94DF04-low.png
 
Figure 7-12 DIDD vs External DVDD
GUID-CC389F14-B708-4B7A-85B9-6F03A2B5473C-low.png
 
Figure 7-14 Internal DVDD PSRR vs Frequency
GUID-C39431FF-EC46-48B1-922F-863C6913A3FC-low.png
 
Figure 7-16 VOUT TUE vs Code
GUID-76E4E322-4C89-405E-8C11-0BB14AE1BB4F-low.png
 
Figure 7-18 VOUT TUE vs Supply
GUID-F125F0A0-BF1E-48B4-860C-DB27947B2E05-low.png
 
Figure 7-20 VOUT INL vs Code
GUID-19EB56FD-2C05-4774-AA8E-697C93622E40-low.png
 
Figure 7-22 VOUT INL vs Supply
GUID-16B5EA09-BA40-475E-B776-45DF7BCBED4F-low.png
 
Figure 7-24 VOUT DNL vs Code
GUID-04534714-C5EB-4D22-8CBF-C90C2F68EFA2-low.png
 
Figure 7-26 VOUT DNL vs Supply
GUID-1A8FFA29-770D-4C2E-9CD7-677DE5D3E516-low.png
 
Figure 7-28 Offset Error vs Temperature
GUID-DBD82597-B3F7-4CC3-9860-B279781797E3-low.png
 
Figure 7-30 Gain Error vs Temperature
GUID-24C7648A-CA20-4955-86B0-A2D68DA711DB-low.png
 
Figure 7-32 VOUT (Full-Scale) vs Load Current (Source or Sink)
GUID-303518BF-6C97-4030-89BA-21F949CB9A18-low.png
 
Figure 7-34 BP10V Rising
GUID-54B24BDB-2D79-4731-ABC9-59D4A0D65ACD-low.png
 
Figure 7-36 VOUT Settling Time vs Load
(No Compensation Capacitor)
GUID-8497A20F-9559-45BD-8632-8D253994EC71-low.png
 
Figure 7-38 VOUT Settling Time vs LOAD
(470 pF Between VOUT and CMP Pins)
GUID-2E3F9709-A3AB-4E64-9A1A-47C54C3FE744-low.png
 
Figure 7-40 VOUT Digital-to-Analog Glitch
GUID-8B8C16A2-B054-42F2-850C-317C2C0F3C22-low.png
 
Figure 7-42 VOUT, Peak-to-Peak Noise (0.1 Hz to 10 Hz)
GUID-9BA41C09-FD1C-4062-8876-4081AF44212D-low.png
 
Figure 7-44 VOUT Short-Circuit Current vs Temperature
GUID-3D436C7E-DB61-4FFB-9B0D-29CF74DA02AD-low.png
 
Figure 7-46 IOUT TUE vs Code (0 mA to 24 mA)
GUID-089ADF3E-B6DE-47FD-B4FD-D3EDF6AEC105-low.png
 
Figure 7-48 IOUT TUE vs Code (4 mA to 20 mA)
GUID-4D68778C-8BAA-4D47-96B1-CA7B27AE4541-low.png
 
Figure 7-50 IOUT TUE vs Temperature (External RSET)
GUID-F65B7534-5438-480C-AAE8-1934A4093C9E-low.png
 
Figure 7-52 IOUT TUE vs Supply (External RSET)
GUID-CD1E19A5-764B-4EC2-A646-E5C2789BB77B-low.png
 
Figure 7-54 IOUT INL vs Code (0 mA to 20 mA)
GUID-78ADE317-52E9-46D0-A1FB-E9F4BA57E093-low.png
 
Figure 7-56 IOUT INL vs Temperature (Internal RSET)
GUID-39E85E66-711B-4CC1-9178-F45CEFC92E13-low.png
 
Figure 7-58 IOUT INL vs Supply (Internal RSET)
GUID-6506E04B-A903-48BC-9C43-4CE830B3DD60-low.png
 
Figure 7-60 IOUT DNL vs CODE (0 mA to 24 mA)
GUID-D2EA1458-57B7-4D4D-9B20-989A224F8036-low.png
 
Figure 7-62 IOUT DNL vs Code (4 mA to 20 mA)
GUID-BD238A01-E053-4BA7-BA1C-FFAA44272F1C-low.png
 
Figure 7-64 IOUT DNL vs Temperature (External RSET)
GUID-E0F2FA5D-F316-41F4-BA24-64B380D18B16-low.png
 
Figure 7-66 IOUT DNL vs Supply (External RSET)
GUID-AFC4C7B1-2196-48B7-A54C-D61EFA661CC3-low.png
 
Figure 7-68 IOUT Offset Error vs Temperature
GUID-B8496D0E-CBCB-4A52-ACBF-725C65A8A91A-low.png
Compliance voltage headroom is defined as the drop from AVDD pin to the IOUT pin.
Figure 7-70 Compliance Headroom Voltage(1) vs Temperature
GUID-B393FCD6-9552-4BC5-9FD0-E7F41B44E51A-low.png
 
 
Figure 7-72 4-mA to 20-mA Rising
GUID-AA6AAD4A-EA05-4FB1-A14E-E8737DEC6E73-low.png
 
Figure 7-74 IOUT Power-On Glitch
GUID-EE280980-63C5-423E-8B6F-6A5CAADF7D81-low.png
 
Figure 7-76 IOUT Digital-to-Analog Glitch
GUID-0D9F5C14-114A-464B-9983-487ECAD52EB0-low.png
 
Figure 7-78 IOUT Peak-to-Peak Noise vs Time (0.1 Hz to 10 Hz)
GUID-92F89BA1-9090-4CC5-8A2C-9EEA5B83AA04-low.png
 
Figure 7-80 IOUT PSRR vs Frequency