JAJSM76E December   2015  – August 2022 LMX2582

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Functional Description
      1. 7.3.1  Input Signal
      2. 7.3.2  Input Signal Path
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N Divider and Fractional Circuitry
      5. 7.3.5  Voltage Controlled Oscillator
      6. 7.3.6  VCO Calibration
      7. 7.3.7  Channel Divider
      8. 7.3.8  Output Distribution
      9. 7.3.9  Output Buffer
      10. 7.3.10 Phase Adjust
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Down
      2. 7.4.2 Lock Detect
      3. 7.4.3 Register Readback
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power on Programming Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
    6. 7.6 Register Maps
      1. 7.6.1 LMX2582 Register Map – Default Values
        1. 7.6.1.1 Register Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1  Optimization of Spurs
        1. 8.1.1.1 Understanding Spurs by Offsets
        2. 8.1.1.2 Spur Mitigation Techniques
      2. 8.1.2  Configuring the Input Signal Path
        1. 8.1.2.1 Input Signal Noise Scaling
      3. 8.1.3  Input Pin Configuration
      4. 8.1.4  Using the OSCin Doubler
      5. 8.1.5  Using the Input Signal Path Components
        1. 8.1.5.1 Moving Phase Detector Frequency
        2. 8.1.5.2 Multiplying and Dividing by the Same Value
      6. 8.1.6  Designing for Output Power
      7. 8.1.7  Current Consumption Management
      8. 8.1.8  Decreasing Lock Time
      9. 8.1.9  Modeling and Understanding PLL FOM and Flicker Noise
      10. 8.1.10 External Loop Filter
    2. 8.2 Typical Application
      1. 8.2.1 Design for Low Jitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 サポート・リソース
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Typical Characteristics

TA = 25°C (unless otherwise noted)

GUID-4202BE2B-FBDB-4A25-BD1E-0E63689ABBBE-low.gif
Figure 6-2 900-MHz Output - Closed-Loop Phase Noise
GUID-362D4422-FBD8-4CDE-91C1-92102B0C677B-low.gif
Figure 6-4 1.8-GHz Output - Closed-Loop Phase Noise
GUID-F79CC21A-B543-4CB4-91AF-50104751CF53-low.gif
Figure 6-6 5.5-GHz Output - Closed-Loop Phase Noise
GUID-0669A3B4-780E-43D0-99B4-0F6631110799-low.gif
Figure 6-8 Integrated Jitter (47 fs) - 1.8-GHz Output
GUID-A1C64102-F7AE-41DC-AF6C-045496B69AF7-low.gif
Figure 6-10 Variation of Phase Noise Across Temperature
GUID-AD654F1D-7148-4C5E-A4CD-85AD36053B08-low.gif
Figure 6-12 High Output Power (50-Ω Pullup, Single-Ended) vs Output Frequency
GUID-92E4FD3F-83A2-4969-B675-FE5C13AAFC8B-low.gif
Figure 6-14 Typical PFD Spur for 5.4-GHz Output
GUID-01D9577B-6F66-4E68-BF7C-BC46E97CFB2F-low.gif
Figure 6-16 Impact of Channel Divider Settings on Phase Noise
GUID-D8CAE042-6FE6-4BD8-B6F3-C812DB6FE21C-low.gif
Figure 6-3 900-MHz Output - Open-Loop Phase Noise
GUID-6EFD3639-6CEF-4633-A15A-37B4C762C0F7-low.gif
Figure 6-5 1.8-GHz Output - Open-Loop Phase Noise
GUID-6C2E2B12-9FFB-4291-80F4-CACE8128F486-low.gif
Figure 6-7 5.5-GHz Output - Open-Loop Phase Noise
GUID-25289643-6E3B-40A6-BF0A-926CEAEF3992-low.gif
Figure 6-9 5.4-GHz Output Wide Loop Bandwidth – Showing PLL Performance
GUID-E68D495D-07E8-4D34-90C9-5BAD1E27B2C8-low.gif
Figure 6-11 Impact of Supply Ripple on 1.8-GHz Output Phase Noise
GUID-288AF872-3252-4593-9BB8-597D45B01138-low.gif
Figure 6-13 Output Power at 5.4-GHz Output vs OUTx_POW Code (1 - 31, 48 - 63)
GUID-0C344627-63BD-435E-8CFF-7A9A592FB49C-low.gif
Figure 6-15 20-µs Frequency Change Time to 1.8 GHz With Fast Calibration
GUID-BB55E0EC-F57F-4A76-B40D-D2078343EEBE-low.gif
Figure 6-17 Noise Floor Variation With Output Frequency