The TPS629210-Q1 is optimized to work within a range of external components. The LC output filters inductance and capacitance have to be considered together, creating a double pole, responsible for the corner frequency of the converter. See the TPS629210-Q1 data sheet for more details.

The TIDA-050056 is designed with a nominal 1.5-μH inductor to support 3.3-V output voltage. A shielded wire-wound inductor from Murata (DFE201210U-1R5=P2) is used in this design. It has 2.5-A saturation current and 138-mΩ maximum DCR. 1.5-μH inductance is ideal for size and ripple given the VOUT of this 3.3-V design. The larger values can be used to achieve a lower inductor ripple current but they can have a negative impact on efficiency and transient response. Small values that 1.5-μH will cause a larger inductor ripple current which causes a larger negative inductor current in forced PWM mode at low or no output current.

A small low equivalent series resistance(ESR) multilayer ceramic capacitor(MLCC) is recommended to obtain the best filtering. Fro this design, a 10-μF /25-V multilayer ceramic chip capacitor from Murata (GRM188R61E106MA73L) is used as an input capacitor. It is designed to withstand up to 25-V which is enough for input voltage range that we want to cover in this design.

For the output capacitor, the voltage rating is much smaller than the input, only 6-V to 10-V capacitor rating is needed. A 22-μF/10-V multilayer ceramic chip capacitor from Murata( GRM188R61A226ME15D) is chosen.

The MODE/S-CONF requires an E96 resistor series, 1% accuracy, temperature coefficient better or equal than ±200-ppm/°C. A small size 0402 package (CRCW040227K4FKED) from Vishay is used in this design.