SBAA483 February   2021 ADS1120 , ADS112C04 , ADS112U04 , ADS114S06 , ADS114S06B , ADS114S08 , ADS114S08B , ADS1220 , ADS122C04 , ADS122U04 , ADS124S06 , ADS124S08 , ADS125H02 , ADS1260 , ADS1261 , ADS1262 , ADS1263

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Features Used to Detect Wire Breaks in RTD Systems
    1. 2.1 Detecting a Wire Break Using a Continuous VREF Monitor
    2. 2.2 Detecting a Wire Break Using a Periodic VREF Monitor
    3. 2.3 Detecting a Wire Break Using Separate Analog Inputs
  5. 3Wire-Break Detection Methods for Different RTD Configurations
    1. 3.1 Wire-Break Detection Using 2-Wire RTDs
    2. 3.2 Wire-Break Detection Using 3-Wire RTDs
      1. 3.2.1 Wire-Break Detection in a One-IDAC, 3-Wire RTD System
        1. 3.2.1.1 Detecting a Break in Lead 2 in a One-IDAC, 3-Wire RTD System
          1. 3.2.1.1.1 Detecting a Break in Lead 2 in a One-IDAC, 3-Wire RTD System Using a High-Side RREF
        2. 3.2.1.2 Wire-Break Detection Summary for a One-IDAC, 3-Wire RTD System
      2. 3.2.2 Wire-Break Detection in a Two-IDAC, 3-Wire RTD System
        1. 3.2.2.1 Detecting Lead 1 or 2 breaks in a two IDAC, 3-wire RTD system using a low-side RREF
        2. 3.2.2.2 Detecting Lead 1 or 2 Breaks in a Two-IDAC, 3-Wire RTD System Using a High-Side RREF
        3. 3.2.2.3 Wire-Break Detection Summary for a Two-IDAC, 3-Wire RTD System
    3. 3.3 Wire-Break Detection in a 4-Wire RTD System
      1. 3.3.1 Detecting Lead 2 and Lead 3 Breaks in a 4-Wire RTD System Using a Low-Side RREF
      2. 3.3.2 Detecting Lead 2 and Lead 3 Breaks in a 4-Wire RTD System Using a High-Side RREF
      3. 3.3.3 Wire-Break Detection Summary for a 4-Wire RTD System
  6. 4Settling Time Considerations for RTD Wire-Break Detection
  7. 5Summary
  8.   A How Integrated PGA Rail Detection Helps Identify Wire Breaks
  9.   B Pseudo-Code for RTD Wire-Break Detection
    1.     B.1 Pseudo-Code for a 2-Wire RTD System (Low-Side or High-Side RREF)
    2.     B.2 Pseudo-Code for a One-IDAC, 3-Wire RTD System (Low-Side or High-Side RREF)
    3.     B.3 Pseudo-Code for a Two-IDAC, 3-Wire RTD System (Low-Side or High-Side RREF)
    4.     B.4 Pseudo-Code for a 4-Wire RTD System (Low-Side or High-Side RREF)

How Integrated PGA Rail Detection Helps Identify Wire Breaks

Although wire-break detection can be implemented using IDACs and VREF monitoring as described throughout this document, some ADCs integrate additional features to make wire-break detection easier.

One such feature is PGA rail detection, which allows the user to detect if the PGA output (or input, in some cases) is operating too close to the supply rails. This feature can be used to identify wire breaks because AINP or AINN can be pulled to AVDD when the IDAC no longer has a path to ground, as shown in Figure A-1. This feature can be employed during a diagnostic measurement routine to more accurately determine which pin has broken.

GUID-20210107-CA0I-DK9H-LK14-9VBNNMP06DZP-low.gifFigure A-1 PGA Rail Detection Identifies Overranged Inputs

The ADS124S08 is an example of an ADC that integrates PGA rail detection features. If the level of the ADS124S08 PGA output voltage exceeds AVDD – 0.15 V, or drops below AVSS + 0.15 V, the ADC sets a flag to indicate that the output has gone beyond the output range of the PGA. Each PGA output (OUTN and OUTP) can trigger an overvoltage or undervoltage flag, giving a total of four flags:

  • FL_P_RAILP (bit 5 of the STATUS byte): VOUTP has exceeded AVDD – 0.15 V
  • FL_P_RAILN (bit 4 of the STATUS byte): VOUTP dropped below AVSS + 0.15 V
  • FL_N_RAILP (bit 3 of the STATUS byte): VOUTN has exceeded AVDD – 0.15 V
  • FL_N_RAILN (bit 2 of the STATUS byte): VOUTN dropped below AVSS + 0.15 V

For more information about the PGA rail detection features in a specific ADC, see that ADC data sheet. Table A-1 can also be referenced for a quick comparison of available features integrated into the precision delta-sigma ADCs highlighted in Table 1-1.

Table A-1 Summary of PGA Rail Detection Features in Precision ΔΣ ADCs
DevicePGA Rail Detection Flags
ADS1120N/A
ADS112C04
ADS112U04
ADS1220
ADS122C04
ADS122U04
ADS114S06B
  • PGA positive output (OUTP) is too close to AVDD
  • PGA positive output (OUTP) is too close to AVSS
  • PGA negative output (OUTN) is too close to AVDD
  • PGA negative output (OUTN) is too close to AVSS
ADS114S08B
ADS114S06
ADS114S08
ADS124S06
ADS124S08
ADS125H02
  • PGA positive input (INP) is too close to HVDD
  • PGA positive input (INP) is too close to HVSS
  • PGA negative input (INN) is too close to HVDD
  • PGA negative input (INN) is too close to HVSS
  • PGA positive output (OUTP) is too close to HVDD
  • PGA positive output (OUTP) is too close to HVSS
  • PGA negative output (OUTN) is too close to HVDD
  • PGA negative output (OUTN) is too close to HVSS
ADS1260
  • PGA positive/negative output (OUTx) is too close to AVDD
  • PGA positive/negative output (OUTx) is too close to AVSS
ADS1261
ADS1262
  • PGA positive/negative output (OUTx) is too close to AVDD
  • PGA positive/negative output (OUTx) is too close to AVSS
  • PGA differential output > FS
ADS1263