By default, the EVM is configured to use LMX->DACCLK | LMX/LMK->FPGA clock option. The user provide a single high freqeuncy(8-10dBm) signal to an SMA labled LMX CLKp. This signal is routed to LMX1204 which generates the buffered DACCLK signal, low freqeuncy DAC SYSERF signal, FPGA reference clocks and FPGA SYSREF signal. The FPGA reference clocks and FPGA SYSREF signal are feed into the CLKIN1 and CLKIN0 of LMK04828. The LMK04828 and is used in clock distribution mode and provides several copies/divided down version of FPGA reference clock and FPGA SYSREF signal.

The EVM can be configured to use LMX->DACCLK | LMX/LMK->FPGA clock option with the following steps:

1. Modify the hardware:
   1. Remove C136 and C139, populate C141 and C142.
   2. Remove C134 and C135, populate C138 and C140
   3. Remove C75 and C76, populate C73 and C74