SBAU407 april   2023 ADS8354

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
    1. 1.1 ADS8354EVM-PDK Features
    2. 1.2 ADS8354EVM Features
    3. 1.3 Related Documentation From Texas Instruments
  4. 2Analog Interface
    1. 2.1 Connectors for Analog Inputs
    2. 2.2 ADC Input Signal Driver
      1. 2.2.1 Input Signal Path
  5. 3Digital Interfaces
    1. 3.1 SPI for the ADC Digital I/O
  6. 4Power Supplies
    1. 4.1 ADC Input Driver Configuration
    2. 4.2 ADC Voltage Reference Configuration
  7. 5ADS8354EVM-PDK Initial Setup
    1. 5.1 Default Jumper Settings
    2. 5.2 EVM Graphical User Interface Software Installation
  8. 6ADS8354EVM-PDK Operation
    1. 6.1 EVM GUI Global Settings for ADC Control
    2. 6.2 Time Domain Display Tool
    3. 6.3 Spectral Analysis Tool
    4. 6.4 Histogram Analysis Tool
  9. 7Bill of Materials, Printed-Circuit Board Layout, and Schematics
    1. 7.1 Bill of Materials
    2. 7.2 PCB Layout
    3. 7.3 Schematics

3.1 SPI for the ADC Digital I/O

The ADS8354EVM-PDK supports the interface and ADC input modes detailed in the ADS8354 data sheet. The PHI is capable of operating at a 3.3-V logic level and is directly connected to the digital I/O lines of the ADC.

As shown in Figure 3-3, a debug header (J5) with the digital I/O lines is included on the ADS8354EVM. This header can facilitate connections to logic analyzer probes, oscilloscope probes, or external controllers.

GUID-20230331-SS0I-3HD2-5LWF-R9JKT4CT8CCJ-low.svg Figure 3-1 ADS8354EVM Debug Header