SBAU412A November   2022  – May 2024 AFE7900 , AFE7903 , AFE7906 , AFE7920 , AFE7921 , AFE7950

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Prerequisites
  6. 3 Typical Bare-Metal Design Flow
  7. 4 Background
  8. 5 Add Microblaze and SPI IP for Use in Vitis for Embedded Development
  9. 6 Create New Platforms in Vitis
  10. 7 Create New Application Projects in Vitis
  11. 8 Build Application Projects
  12. 9 Generate SPI Log for AFE79xx EVM
    1. 9.1 Generating the LMK SPI Log
    2. 9.2 Generating the AFE SPI Log
    3. 9.3 Converting SPI Logs to Format for Vitis
  13. 10AFE79xxEVM Board Modifications
  14. 11Configure the AXI GPIO
    1. 11.1 Initializing the GPIO
    2. 11.2 Setting the Direction
    3. 11.3 Setting High or Low for Corresponding Bits
  15. 12Configure the AXI SPI
  16. 13Set Up and Power on Hardware
  17. 14Set up ZCU102 Board Interface for VADJ_FMC
  18. 15Debug Application Projects and Set up Vitis Serial Terminal
  19. 16Execute the Application
  20. 17Revision History

5 Add Microblaze and SPI IP for Use in Vitis for Embedded Development

  1. Open an existing Vivado project or create a new one.
  2. Under the ‘IP Integrator’ in the left pane, click ‘Create Block Design’.
    AFE7920 Creating Block Design Figure 5-1 Creating Block Design
  3. Give a name to the block design and click ‘OK’.
    AFE7920 Name the Block Design Figure 5-2 Name the Block Design
  4. In the newly created block design, click ‘+’ to add IP.
    AFE7920 Adding IP to Block Design Figure 5-3 Adding IP to Block Design
  5. Search for Microblaze and add ‘Microblaze’ to block design.
    AFE7920 Adding Microblaze to Block Design Figure 5-4 Adding Microblaze to Block Design
  6. Click ‘Run Block automation’ and then ‘OK’.
    AFE7920 Run Block Automation for Microblaze Figure 5-5 Run Block Automation for Microblaze
  7. Several IP blocks companions to Microblaze are automatically added by Vivado.
  8. Click ‘Run Connection automation’.
  9. In the Connection Automation pop-up, select ‘CLK_IN1_D’, map it to ‘user_si570_sysclk’ and click ‘OK’.
    AFE7920 CLKIN for Microblaze Figure 5-6 CLKIN for Microblaze
  10. Click ‘Run Connection automation’ again.
  11. In the Connection Automation pop-up, select ‘reset’, ‘ext_reset_in’ and map them to ‘reset (FPGA_reset)’ and click ‘OK’.
    AFE7920 Reset Connection for Microblaze Figure 5-7 Reset Connection for Microblaze
  12. Right click block design and add ‘AXI Quad SPI’ as shown in Figure 5-8 and Figure 5-9.
    AFE7920 Adding IP to Block Design Figure 5-8 Adding IP to Block Design
    AFE7920 Adding ‘AXI QUAD SPI’ IP to Block Design Figure 5-9 Adding ‘AXI QUAD SPI’ IP to Block Design
  13. Click ‘Run Connection automation’.
    AFE7920 Running Connection Automation for ‘AXI_LITE’ Figure 5-10 Running Connection Automation for ‘AXI_LITE’
  14. Select ‘AXI_LITE’ and click ‘OK’.
    AFE7920 ‘ext_spi_clk’ Shows No Connection in ‘AXI QUAD SPI’ Figure 5-11 ‘ext_spi_clk’ Shows No Connection in ‘AXI QUAD SPI’
  15. Connect ‘s_axi_aclk’ to ‘ext_spi_clk’.
    AFE7920 ‘ext_spi_clk’ Connected to ‘s_axi_aclk’ Figure 5-12 ‘ext_spi_clk’ Connected to ‘s_axi_aclk’
  16. Double click ‘AXI Quad SPI’ -> select No. of slaves and then click ‘OK’.
    AFE7920 Select Number of SPI Slaves in ‘AXI QUAD SPI’ Figure 5-13 Select Number of SPI Slaves in ‘AXI QUAD SPI’
  17. From the Quad SPI IP, map the signals as following:
    1. ‘io0_o’ -> SPI_SDO
    2. ‘Io1_i’ <- SPI_SDI
    3. ‘sck_o’ -> SPI_SCL
    4. ‘ss_o[1:0] -> SPI_SEN0, SPI_SEN1
  18. The ‘ss_o’ bit width will be based on No. of slaves selected in step:16
    AFE7920 Highlighting Ports for External Connections in ‘AXI QUAD SPI’ Figure 5-14 Highlighting Ports for External Connections in ‘AXI QUAD SPI’
  19. Validate the design to ensure no errors as shown in Figure 5-15.
    AFE7920 Validating Block Design Figure 5-15 Validating Block Design
  20. To add GPIOs, add ‘AXI GPIO’ from catalog and repeat similar steps as above.