The instantaneous I and V signals for each phase are accumulated in 48-bit registers. A cycle tracking counter and sample counter keep track of the number of samples accumulated. When approximately one second of samples have been accumulated, the background process stores these 48-bit registers and notifies the foreground process to produce the average results like RMS and power values. The sample code uses cycle boundaries to trigger the foreground averaging process, because this gives very stable results.

For frequency measurements, the sample code does a straight-line interpolation between the zero-crossing voltage samples. Figure 5-4 shows the samples near a zero crossing and the process of linear interpolation.

Figure 5-4 Frequency Measurement

Because noise spikes can also cause errors, the codes uses a rate-of-change check to filter out the possible erroneous signals and make sure that the points interpolated from are genuine zero-crossing points. For example, with two negative samples, a noise spike can make one of them positive and, therefore, make the negative and positive pair looks as if there were a zero crossing.

The resultant cycle-to-cycle timing goes through a weak low-pass filter to further smooth out cycle-to-cycle variations. This results in a stable and accurate frequency measurement that is tolerant of noise.