SLAAE71 December   2022 MSPM0G1105 , MSPM0G1106 , MSPM0G1107 , MSPM0G1505 , MSPM0G1506 , MSPM0G1507 , MSPM0G3105 , MSPM0G3106 , MSPM0G3107 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
  4. 2Low-Power Features in PMCU
    1. 2.1 Overview
      1. 2.1.1 Power Domains and Power Modes
      2. 2.1.2 Power Management (PMU)
        1. 2.1.2.1 Supply Supervisors
        2. 2.1.2.2 Peripheral Power Control
        3. 2.1.2.3 VBOOST for Analog Muxes
      3. 2.1.3 Clock Module (CKM)
        1. 2.1.3.1 Oscillators
        2. 2.1.3.2 Clocks
      4. 2.1.4 System Controller (SYSCTL)
        1. 2.1.4.1 Asynchronous Fast Clock Requests
        2. 2.1.4.2 Shutdown Mode Handling
  5. 3Low-Power Optimization
    1. 3.1 Low-Power Basics
    2. 3.2 MSPM0 Low-Power Feature Use
      1. 3.2.1 Low-Power Modes
      2. 3.2.2 System Clock and Peripheral Operation Frequency
      3. 3.2.3 I/O Configuration
      4. 3.2.4 Event Manager
      5. 3.2.5 Analog Peripheral Low-Power Features
      6. 3.2.6 Run Code From RAM
    3. 3.3 Software Coding Strategies
    4. 3.4 Hardware Design Strategies
  6. 4Power Consumption Measurement and Evaluation
    1. 4.1 Current Evaluation
    2. 4.2 Current Measurement
      1. 4.2.1 Current Measurement

1 Overview

TI’s scalable MSPM0Gxx series MCU family are based on Arm® Cortex®-M0+ core, with a maximum CPU speed of 80 MHz, which provides the high computation power. The portfolio covers up to 512KB of on-chip flash and up to 128KB on-chip SRAM with extended scalable analog Integration. They also integrate an efficient power supply architecture and various power modes that helps the power consumption reduction and simplify the application design. Its overall low-power performance is show inTable 1-1. For more details, see the device-specific data sheet.

Table 1-1 MSPM0Gxx Series Low-Power Performance
Low-Power ModeMSPM0Gxx
Run(1)(5)85 µA/MHz
Sleep(2)(5)200 µA at 4 MHz
Stop(3)(5)50 µA at 32 kHz
Standby(4)(5)1.5 µA
Shutdown(5)50 nA with IO wakeup capability
(1) MCLK = SYSPLL = 80 MHz, SYSPLLREF = SYSOSC, CoreMark, execute from flash
(2) MCLK = SYSOSC (internal oscillator), CPU is halted
(3) SYSOSC off, DISABLESTOP = 1, ULPCLK = LFCLK
(4) LFCLK = LFXT, STOPCLKSTBY = 1, GPIOA enabled
(5) Typical value at 25°C and VDD = 3.3 V. All inputs tied to 0 V or VDD. Outputs do not source or sink any current. All peripherals are disabled.

This application note helps developers understand the MSPM0Gxx series low-power features, how power can be optimized to meet the specific needs based on MSPM0, and how to evaluate and measure it. The design flow for a low-power design and the limited recommended chapters are shown in Figure 1-1.

Figure 1-1 Low-Power Development Process

Table 1-2 gives a list for items to check related to low-power consumption.

Table 1-2 Low-Power Development Checklist
NumberClassificationItemComment
1 Hardware designMCU power supplyReduce MCU power supply no lower than 1.62V.
2 ResistorsChoose large resistors after meeting system requirement.
3CapacitorsChoose low leakage capacitors.
4Power ICNormally choose a linear regulator.
5Software codingConditional code executionUse a conditional wake-up and code execution structure.
6Nonblocking programmingAvoid blocking mode by using while loop.
7 Optimize code sizeChoose TI Arm Clang, fully use compiler features, and write code with good coding style.
8MSPM0 low-power feature usage Use low-power modesUse different power modes (RUN, SLEEP, STOP, STANDBY, and SHUTDOWN) and three lower mode policy options (XX0, XX1, XX2) according to the application requirements.
9Reduce system clock and peripheral operation frequencyOnly the minimum required system clock frequency. Reduce peripheral operation frequency and turn them off when not used.
10I/O configurationLeave unused pins as default high-Z configuration. Reduce the use of internal pull-up or pull-down resistors. Pay attention to the IO-latch in low-power modes.
11Use event managerUse event manager to realize peripherals trigger DMA or peripherals trigger peripherals to reduce the CPU usage.
12Use analog peripherals low-power featuresCompromise between performance and low-power consumption for the ADC, COMP, OPA, and GPAMP.
13Run code from RAMMove a part of common used code from flash to RAM.