1 Introduction

The TAX5X family permits a wide variety of timings to input to the chip. These timings include standard audio rates as well as non standard rates. The devices detect if the timings are valid and if so, the internal PLL, as well as, dividers are configured automatically. The device also can also return a clock error in case of a change in timing. It is also possible to read the actual input timings through a register

In Automatic configuration the below Fs buckets are recognized as shown in Table 1-1.

By default, only 1% tolerance frequency range is supported in SW pin configuration mode (Table 1-1) which can be extended to support 5% tolerance range (Table 1-2) using B0_P0_R50[1] for PASI and B0_P0_R51[1] for SASI.