This section provides details on the manual SYNC operation of the ADC12DJ3200EVM.

1. In the ADC12DJ3200EVM-CVAL GUI, click on the JESD204B tab as Figure 7-3 shows.
   Figure 7-3 JESD204B Tab
2. Implement the following steps (in order):
   • Click on the "JESD Block Enable" to disable it (the green arrow should not be lit).
   • Click on the SFORMAT button (to enable it). The FPGA firmware is using unsigned data and a K value of 4.
   • Click the JSYNC_N Sync _Request button (it should be enabled or ‘lit’).
   • Select “No SYNC Input Signal” from the SYNC Input Selection drop-down menu.
   Figure 7-4 Setting ADC to use Software SYNC
3. Click on the “JESD Block Enable" (to enable it). The GUI should look now as shown in Figure 7-5.
   Figure 7-5 SYNC is now set low Inside the ADC