SLAU929A April   2024  – June 2025 MSPM0C1104 , MSPM0G3505 , MSPM0G3506 , MSPM0G3507 , MSPM0H3216 , MSPM0L1105 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1304 , MSPM0L1305 , MSPM0L1306 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1MSPM0 Portfolio Overview
    1. 1.1 Introduction
    2. 1.2 Portfolio Comparison of Microchip AVR ATmega and ATiny MCUs to MSPM0
  5. 2Ecosystem and Migration
    1. 2.1 Software Ecosystem Comparison
      1. 2.1.1 MSPM0 Software Development Kit (MSPM0 SDK)
      2. 2.1.2 MPLAB X IDE vs Code Composer Studio IDE (CCS)
      3. 2.1.3 MPLAB Code Configurator vs SysConfig
    2. 2.2 Hardware Ecosystem
    3. 2.3 Debug Tools
    4. 2.4 Migration Process
    5. 2.5 Migration and Porting Example
  6. 3Core Architecture Comparison
    1. 3.1 CPU
    2. 3.2 Embedded Memory Comparison
      1. 3.2.1 Flash Features
      2. 3.2.2 Flash Organization
        1. 3.2.2.1 Memory Banks
        2. 3.2.2.2 Flash Memory Regions
        3. 3.2.2.3 NONMAIN Memory
      3. 3.2.3 Embedded SRAM
    3. 3.3 Power Up and Reset Summary and Comparison
    4. 3.4 Clocks Summary and Comparison
    5. 3.5 MSPM0 Operating Modes Summary and Comparison
      1. 3.5.1 Operating Modes Comparison
      2. 3.5.2 MSPM0 Capabilities in Lower Power Modes
      3. 3.5.3 Entering Lower-Power Modes
    6. 3.6 Interrupt and Events Comparison
      1. 3.6.1 Interrupts and Exceptions
      2. 3.6.2 Event Handler and EXTI (Extended Interrupt and Event Controller)
    7. 3.7 Debug and Programming Comparison
      1. 3.7.1 Bootstrap Loader (BSL) Programming Options
  7. 4Digital Peripheral Comparison
    1. 4.1 General-Purpose I/O (GPIO, IOMUX)
    2. 4.2 Universal Asynchronous Receiver-Transmitter (UART)
    3. 4.3 Serial Peripheral Interface (SPI)
    4. 4.4 I2C
    5. 4.5 Timers (TIMGx, TIMAx)
    6. 4.6 Windowed Watchdog Timer (WWDT)
    7. 4.7 Real-Time Clock (RTC)
  8. 5Analog Peripheral Comparison
    1. 5.1 Analog-to-Digital Converter (ADC)
    2. 5.2 Comparator (COMP)
    3. 5.3 Digital-to-Analog Converter (DAC)
    4. 5.4 Operational Amplifier (OPA)
    5. 5.5 Voltage References (VREF)
  9. 6References
  10. 7Revision History

3.1 CPU

The ATmega/ATtiny and MSPM0 families of parts are quite different from each other. These Microchip devices utilize a proprietary 8-bit CPU core, while the MSPM0 devices utilize an ARM M0+ 32-bit core. Table 3-1 gives a high-level overview of the general features of the CPUs in the MSPM0G and MSPM0L families compared to the ATtiny and ATmega devices. Section 3.6.1 provides a comparison of the interrupts and exceptions and how they are mapped in the Nested Vectored Interrupt Controller (NVIC) peripheral included in the M0 architecture for each device.

Table 3-1 Comparison of CPU Feature Sets
Feature ATmega

ATtiny

 MSPM0G MSPM0L MSPM0C
Architecture Microchip 8-bit AVR Microchip 8-bit AVR Arm Cortex-M0+ Arm Cortex-M0+ Arm Cortex-M0+
Maximum MCLK 16MHz 20MHz 32MHz up to 80MHz 32MHz 24MHz/32MHz
CPU instruction cache None None 4 x 64-bit lines (32 bytes) 2 x 64-bit lines (16 bytes) 2 x 64-bit lines (16 bytes)
Processor trace capabilities No No Yes, integrated micro trace buffer No No
Memory protection unit (MPU) No No Yes Yes No
System timer (SYSTICK) No No Yes (24 bit) Yes (24 bit) Yes (24 bit)
NVM prefetch No Yes Yes Yes Yes
Hardware multiply Yes Yes Yes Yes Yes
Hardware breakpoint / watchpoints 0 2 / 0 4/2 2/1 4/2
Boot routine Flash (system memory) Flash (system memory) ROM ROM ROM
Bootstrap loader storage Flash (system memory) Flash (system memory) ROM ROM No
Bootloader interface support(1)(2) Available for all data interfaces Available for all data interfaces UART, I2C,
user extendable		 UART, I2C,
user extendable		 User defined
DMA No No Yes - 12 ch Yes - 7 ch Yes - 3 ch
(1) For availability, see the device-specific data sheet.
(2) Other interfaces to be made available in later device releases.