SLLA535 December 2022 TLIN1431-Q1
The Serial Peripheral Interface (SPI) uses a standard configuration. Physically the digital interface pins are nCS (Chip Select Not), SDI (Serial Data In), SDO (Serial Data Out) and CLK (Serial Clock). Each SPI transaction is 16 bits containing an address and read/write command byte followed by one data byte. If SPI CRC is enabled each transaction is 24 bits containing an address and read/write command byte followed by one data byte and one CRC byte.
Once the SPI is enabled by a low on nCS, the device samples the input data on each rising edge of the SPI clock (CLK). The data is shifted into an appropriately sized shift register and after the correct number of clock cycles the shift register is full and the SPI transaction is complete. For a write command code, the new data is written into the addressed register only after the exact number of clock cycles have been shifted in by CLK and the nCS has a rising edge to deselect the device. If the correct number of clock cycles and data are not shifted in during one SPI transaction (nCS low), interrupts at 8'h50[7], 8'h50[4] and 8'h53[7], SPIERR, is set.