2 SPI Communication

All device configuration takes place through the use of a 4-wire SPI. On the TCAN28xx and TCAN24xx families of devices the four SPI pins are SDO (Serial Data Out), SDI (Serial Data In), CLK (SPI Clock), and nCS (active low chip select line). These are analogous to common SPI signal naming SDO = CIPO (controller in, peripheral out), SDI = COPI (controller out, peripheral in), CLK = SCLK (SPI Clock), and nCS has the same naming convention – this assumes that the SBC is always a peripheral to a main system controller – which is true as these are mid-range SBCs that do not integrate a controller.

The SBCs supports SPI modes 0 through 3, but uses mode 0 as default. The mode changes the CPOL (clock polarity) and CPHA (clock phase) of the SPI communication. CPOL, or clock polarity, sets the default level of the SPI clock – in modes 0 and 1 this is low and in modes 2 and 3 this is set to high. CPHA, or clock phase, deals with when data is sampled and when this is shifted – in modes 0 and 2 data is sampled on rising edge and shifted on a falling edge where modes 1 and 3 can sample on the falling edge and shift on the rising edge.

Figure 2-1 SPI Clocking Vs. SPI Mode

The SBCs use 7-bit addresses for each register and in general unsigned 8-bit integers (uint8_t) need to be used when working with the SPI data on these devices. In general, to perform a write command the base address needs to be shifted left by 1 bit and the new bit in the zero position need to be set to one. If a read operation is to be performed the 7bit address need to be shifted left and the new bit in position 0 need to be set to 0 (if using unsigned integers, the bit shifted in can be 0). An example of a read and write address of a base address of 0x10 is shown in the following.

 uint8_t baseAddress = 0x10;
 uint8_t writeAddress = (baseAddress << 1) | 0x01;
 uint8_t readAddress = (baseAddress <<1) & 0xFE;

The device supports either one byte or two-byte messages – but by default uses one-byte messages.

For one-byte communication – with no CRC included – there are two commands that can be used – a write and a read. The read command starts when nCS pin transitions from low to high and at this time the CLK pin need to see a clock signal on input (in accordance with SPI mode chosen). At the same time the modified read address can be sent to the SDI pin while simultaneously the SDO pin can output the global interrupt vector which gives a high-level view of device operation and potential errors. After the modified address has been sent the SDI line can go quiet and the SDO pin can transmit the contents of the requested register back to the controller. After the register has transmitted the contents to the controller the nCS pin can pull high and the transaction is complete.

Figure 2-2 SPI Read - One Byte Mode

One byte write mode is very similar to the read except the 8th bit sent is 1 instead of 0 to indicate a write action and the data byte is actually sent from the controller to the SBC.

Figure 2-3 SPI Write - One Byte Mode

For two-byte communication the process is very similar to one-byte mode. First – to configure the device for two-byte mode the first SPI transaction can be in the default mode which supports one-byte transactions. To change to two-byte mode, after the device has been started and is in standby mode a write transaction to register 9h must be made with the bit in bit field #3 to be set to 0b1 instead of the 0b0 that is default. This can change the device to two-byte transactions. If other configurations of the SPI are needed, the configurations are mainly contained at register address 9h.

In two-byte mode the SPI communication is still very similar to one-byte mode. Some major differences are as follows. Register writing and reading must be done on sequential registers meaning that if you specify address 10h the two-byte transaction can apply to register 10h and 11h. The second major difference is that SPI speed is no longer limited to 4MHz max, but instead limited to 2MHz max. Each two-byte mode transaction contains 3 discrete byte periods. For two-byte mode read operations the SDI pin receives the 7-bit address and read or write bit for the first byte and is not used for the rest of the transaction; while the SDO pin can output the global interrupt register at the same time as the initial command has been placed then this can be followed by the contents of the register at the selected address further followed by the contents of the register at the selected address + 1. For example, this means that if you are reading register 10h and send command 0b00100000 the SDO pin can respond with register contents for address 10h and 11h while in two-byte mode. Write transactions are also fairly straightforward but the SDI pin can have an input for the entire 3-byte period where the first byte is address + command bit, followed by the data for selected address, finishing with a final byte for the selected address + 1. To exemplify this if you want to write 0xFF and 0xAA respectively to registers 10h and 11h the write command can have the first byte be 0b00100001, with the second byte 0b11111111, followed by 0b10101010.

Figure 2-4 SPI Read - Two Byte Mode

Figure 2-5 SPI Write - Two Byte Mode

The final main transaction type allowed by the TCAN28xx and TCAN24xx lines of devices is one-byte mode + CRC which has transactions that take up a 3-byte time period. The device must be in one-byte mode with CRC enabled to allow for this configuration. The device, when SPI CRC is enabled, supports CRC8H2F, which takes the form X^8 + X^5 + X^3 + X^2 + X + 1 but can be configured to support CRC8 SAE J1850. For the one-byte CRC write operation this starts exactly the same as a typical one-byte write transaction, but after the data that was sent to the register has been transferred a 8-bit CRC of the address + R/W bit + data is input into the device where the SDO pin reads back the global interrupt vector, the previous data, and includes an 8-bit CRC of the global interrupt vector. The read transaction is a bit different – this is initiated in the same way as a one-byte SPI transaction, but instead of not expecting any input after the initial address and R/W bit have been transmitted a filler byte of 0x00 is sent followed by an 8-bit CRC of address + R/W bit + filler byte while the SDO pin can send the global interrupt vector, followed by the contents of selected register, finally followed by 8-bit CRC of the global interrupt vector and data of the selected register. This option can be needed in systems where data integrity on the SPI bus between controller and SBC is critical to system requirements and application success.

Figure 2-6 SPI Read - One Byte Mode + CRC

Figure 2-7 SPI Write - One Byte Mode + CRC

The type of transaction is not the only consideration when configuring SPI with the TCAN28xx and TCAN24xx lines of devices – as this device supports SPI modes 0, 1, 2, and 3 in addition to the variance of transaction type. The SPI mode is independent of the transaction type and this concerns the clock idle polarity (CPOL) as well as the clock phase (CPHA). By default, the SBC is in SPI mode 0, which is the most common form of the SPI bus, in this mode CPOL = 0 which means the clock has an idle state of low and CPHA = 0 meaning that the data is sampled on the rising edge of the clock signal. However, the other modes 2, 3, and 4 can vary the different combinations of CPOL and CPHA – where if CPOL = 1 then the idle state of high and if CPHA = 1 then the data is sampled on the falling edge of the clock.

That covers the basics of communicating with this line of SBCs through a 4-wire SPI bus – the next section covers the basic structure of the registers within device family.