The watchdog timer is one of the more complex systems within the SBC as when SW pin is not held in an active state the watchdog registers lock and there is only a brief period of time to configure the four main watchdog registers.

Figure 6-1 WD Locking Mechanism

The watchdog registers are unlocked upon entry into standby mode and remain unlocked until the watchdog trigger for the initial long window watchdog has occurred or the SBC transitions to normal mode. The four registers that are subject to this locking are WD_CONFIG_1 (address 13h), WD_CONFIG_2 (address 14h), WD_RST_PULSE (address 15h), and WD_QA_CONFIG (address 2Dh). There is enough time to write to all four registers before the transmission of the watchdog trigger to address 15h during the long window period upon entering standby.

For the following example the watchdog can be configured as such:

1. Watchdog is set to QA
2. Watchdog prescaler is set to factor 1
3. Watchdog is disabled in sleep mode
4. Watchdog is disabled in standby (this doesn’t override the long window watchdog upon entry to standby)
5. The long window duration needs to be set to 1000ms
6. For QA watchdog is suggested to have a window size of at least 64ms.
7. QA watchdog can have default feedback, polynomial configuration, and polynomial seed value.
8. Watchdog error count needs to be set to 0 so that if 1 missed watchdog occur an action can be taken (in this case transition to restart mode)

With the configuration goal described the following configuration flow needs to be implemented.

1. Write configuration to WD_CONFIG_1 (address 13h)
   1. Bit Field 7:6 gives watchdog options (disabled, timeout, window, or QA) – QA is represented by 0b11.
   2. Bit Field 5:4 gives 4 prescaler options (factor 1 through factor 4) – factor 1 is represented by 0b00
   3. Bit Field 3 when set enables watchdog in sleep mode; this can be kept default as the example has watchdog disabled in sleep mode.
   4. Bit field 2 sets the standby watchdog type, after the initial long window, which is either timeout or matches the type chosen in bit field 7:6. An important note however is that standby watchdog is disabled in another location – so this can be kept default.
   5. Bit field 1:0 represents the length of the long window upon entry into standby mode with the following options: 150ms, 300ms, 600ms, 1000ms. 1000ms is represented by 0b11
   6. Putting all the bit fields together means that the byte 0xC3 need to be written to address 13h.
2. Write configuration to WD_CONFIG_2 (address 14h)
   1. Bit field 7:5 represents the window (for window and QA) or timeout delay. The window uses this value and the prescaler to determine window size, please see data sheet for full table. Since the minimum recommended for QA is 64ms and there is a factor 1 prescaler that means the smallest configuration option is 128ms which is represented by 0b010 in this field. If 64ms must be hit then the prescaler needs to be set to factor 2 and this field needs to be set to 0b001.
   2. Bit field 4-1 is a read only register that gives the watchdog error counter value.
   3. Bit field 0 when set can disable watchdog in standby (but not the long window up entry into standby) so this needs to be set to 0b1 in this example.
   4. Putting all the bit fields together means that the byte 0x41 needs to be sent to register address 14h
3. Write configuration to WD_RST_PULSE (address 16h)
   1. Bit field 7:4 represents the watchdog error threshold that sets the limit before SBC responds to watchdog error. This can be kept at the default 0b0000 so that every watchdog failure result in SBC action – typically means restarting device.
   2. Bit field 3:0 represents the restart counter; this is read or write 1 to clear and shows how many times the device has reset.
   3. This register can be kept at the default 0x00 for this example and no further configuration is needed.
4. Write configuration to WD_QA_CONFIG (address 2Dh)
   1. Bit field 7:6 represents the feedback settings of the WD QA expected answer block. This is kept to default 0b00 in this example.
   2. Bit field 5:4 represents the QA polynomial configuration and can remain as the default value of 0b00 in this example.
   3. Bit field 3:0 represents the QA polynomial seed and can remain as the default value of 0b1010in this example.
   4. This address can stay default value (0x0A) and no further action is needed.
5. The watchdog configuration is now complete.