SLUAAC5 August 2021 UCC28700 , UCC28701 , UCC28702 , UCC28703 , UCC28704 , UCC28710 , UCC28711 , UCC28712 , UCC28713 , UCC28720 , UCC28722 , UCC28730 , UCC28740 , UCC28742 , UCC28910 , UCC28911

5 Output Overvoltage (OVP) Protection

These flyback controllers sense the output voltage on V_AUX through a resistor divider formed by R_S1 and R_S2 and flyback controller's sense pin (VS). If the VS pin exceeds the V_OVP threshold for three consecutive switching cycles the controller determines that an OVP event has occurred and gate driver switching stops.

Equation 9.

V_{O V P} = 4.6 V

Equation 10.

V_{O U T} \geq \frac{V_{O V P} \times (R_{S 1} + R_{S 2})}{R_{S 2}} \times \frac{N_{S}}{N_{A}}

The schematic in Figure 1-1 represents a flyback converter that was designed to step down an input voltage (V_IN) of 75 V to 390 V DC to a regulated 12 V, 10 W output. The N_S/N_A turns ratio used in this design was 1. In this example, the flyback converter shuts down if V_OUT for three consecutive switching cycles is greater than 13.6 V triggering OVP protection, Equation 11.

Equation 11.

V_{O U T} \geq \frac{4.6 V \times (26.1 k Ω + 51.1 k Ω)}{26.1 k Ω} \times 1 = 13.6 V

If an OVP fault is detected DRV switching stops and the C_DD capacitor is discharged down to V_VDD(off). The C_DD capacitor trickle charges through R_T until V_CDD reaches V_VDD(on). At this point the controller gives three DRV sample pulses at f_SW(max) controlling the primary current to I_PP(max) /4 and t_{LK_RESET} blanking is set to its minimum of 750 ns. Remember that VS will detect an OVP from the end of T_{LK_RESET}to the end of t_DMAG . Refer to Figure 3-1 and Figure 3-2 for details. The CDD and DRV behavior during an OVP fault behaves in similar to UVLO fault presented in Figure 4-1.