SLUAAT7 January   2024 BQ25672 , BQ25790 , BQ25792 , BQ25798

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2IRMS Discharge Current
  6. 3External Battery FET
  7. 4Charger With PG and or Host GPIO
  8. 5Buck-only Charger
  9. 6Boosting Charger
  10. 7Summary
  11. 8References

External Battery FET

Unfortunately, the system load duty cycle is not always known or varies significantly. So, adding an external battery PMOS FET (PFET) powered by the battery and in parallel with the charger's internal battery FET (BATFET) can be necessary. The external PFET turns on when the charger is in sleep or HiZ mode (for example, when the charger has no valid input power). The PFET does not turn on to provide supplement current if the converter enters DPM at maximum input power. The PFET's drain to source voltage rating, VDS, must be higher than the difference between the charger's maximum SYS pin voltage (usually only slightly higher than the battery regulation voltage) and the minimum BAT pin voltage, which can zero if the pack protector opens. In addition, the PFET's gate to source voltage rating, VGS, must be high enough to withstand the maximum battery voltage or a resistor divider or zener diode clamp must be added to protect the PFET's gate. The PFET’s RDSon must be at least as low as the internal battery FET RDSon if not lower. The FET’s maximum threshold voltage (VGSth-max) can also be at least 0.5 V below the lowest battery voltage that is expected to power the FET. For example, the BQ25798's BATFET has RDSon of 8 mΩ typical. If the BQ25798 is configured for battery voltage up to 16.8 V maximum and not lower than 10 V minimum, Alpha and Omega's AONR21357 in 3 mm x 3 mm 8-DFN-EP package with RDSon = 7.8 mΩ at VGS = -10 V is a good choice for external, parallel BATFET for a 2S application. The PFET's source to gate pullup resistor (RPU) must be sized large enough to reduce battery leakage (for example, in the MΩ range) when there is no load on SYS but not too large (for example, > 10 MΩ) for the FET’s gate leakage (if significant) to cause a significant voltage drop.