SLUU194A May   2004  – March 2022 TPS51020

 

  1.   Trademarks
  2. 1Introduction
  3. 2Electrical Performance Specifications
    1. 2.1 Performance Specification Summary
  4. 3TPS51020EVM-001 Circuit Module Schematic
  5. 4Test Setup and Results
    1. 4.1 Test Setup
    2. 4.2 Power Up and Power Down
    3. 4.3 Efficiency and Power Loss
    4. 4.4 Output Ripple
    5. 4.5 Load Transient
    6. 4.6 Loop Characteristics
  6. 5Assembly Drawing and PCB Layout
  7. 6Circuit Module List of Materials
  8. 7References
  9. 8Revision History

Power Up and Power Down

Figure 4-2 and Figure 4-3 show the power-up and power-down waveforms. The power good (PGOOD) pin jumps to high after both outputs have started and have been in regulation for 2048 clock pulses (6.8 ms).

GUID-20220310-SS0I-MHSF-LLLV-1RW7SSNFTPQW-low.pngFigure 4-2 Power-Up Waveform
GUID-20220310-SS0I-8HS5-WBT5-X77NGL0B5ZNQ-low.pngFigure 4-3 Power-Down Waveform