SLUUCV8A October   2023  – June 2025 TPS4810-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Overview
    2. 2.2 General Configurations
      1. 2.2.1 Physical Access
      2. 2.2.2 Test Equipment and Setup
  8. 3Implementation Results
    1. 3.1 Test Setup and Procedures
      1. 3.1.1 Power-up with EN Control
      2. 3.1.2 Overload and Short Circuit Protection Test
      3. 3.1.3 Short-Circuit Protection Diagnosis Test
      4. 3.1.4 Input Reverse Polarity Test
  9. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
    3. 4.3 Bill Of Materials (BoM)
  10. 5Additional Information
    1.     Trademarks
  11. 6Revision History

4.2 PCB Layout

Figure 4-2 shows component placement of the EVAL Board, and Figure 4-4 and Figure 4-6 show PCB layout images.

TPS4810Q1EVM TPS4810Q1EVM Board Top Overlay Figure 4-2 TPS4810Q1EVM Board Top Overlay
TPS4810Q1EVM TPS4810Q1EVM Board Bottom Overlay Figure 4-3 TPS4810Q1EVM Board Bottom Overlay
TPS4810Q1EVM TPS4810Q1EVM Board Top Layer Figure 4-4 TPS4810Q1EVM Board Top Layer
TPS4810Q1EVM TPS4810Q1EVM Board Inner Signal Layer Figure 4-6 TPS4810Q1EVM Board Inner Signal Layer
TPS4810Q1EVM TPS4810Q1EVM Board Bottom LayerFigure 4-5 TPS4810Q1EVM Board Bottom Layer
TPS4810Q1EVM TPS4810Q1EVM Board Inner Routing LayerFigure 4-7 TPS4810Q1EVM Board Inner Routing Layer