SLVA275C january 2010 – may 2023 UCD9081
During three command operations, the UCD9081 holds SCL low while an erase is being performed. The UCD9081 performs an erase just after the WDATA register is written with 0xBADC. See the following UCD9081 data sheet sections for detailed explanation of when the WDATA register is written with 0xBADC.
After an erase, the I2C master may either wait for SCL to be released or wait approximately 12 ms before issuing another transaction.