SLVAG05 October   2025 TPS7A56 , TPS7A57 , TPS7A94 , TPS7A96

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction to LDO Noise and Noise Measurement
    1. 1.1 LDO Noise and LDO Noise Representation
    2. 1.2 Measuring LDO Noise Using a Spectrum Analyzer
  5. 2Solution for Measuring an Ultra-Low Noise LDO (Noise Amplifier Requirements)
    1. 2.1 Estimating the Maximum Noise for the Amplifier
    2. 2.2 Estimating the Amplifier Needed Gain
    3. 2.3 Selecting the Amplifier Circuit Feedback Resistor Values
    4. 2.4 The Amplifier Input/Output DC Blocking Filters
    5. 2.5 Verifying the Designed Amplifier Performance
  6. 3Conclusion
  7. 4References

2.1 Estimating the Maximum Noise for the Amplifier

The starting point for the design of the amplifier is the output noise of the LDO, the DUT. Recent advancements in silicon process technology enable Texas Instruments to deliver an ultra-low noise LDOs. A spectral noise density of 1.3–1.1nV/Hz at 1kHz, and 1nV/Hz (or lower) at 10kHz, can be identified by examining the noise levels of such LDOs. These noise levels are comparable to noise levels offered by current top performing operation amplifier (op-amp) devices. Working back from these levels (using the 10dB margin discussed earlier) an amplifier with input reference noise levels of ≅350pV/Hz and 250pV/Hz at 1kHz and 10kHz, respectively, is necessary, as the 10dB margin suggests. These noise levels equate to noise levels for a transistor (not taking into considering the required BW measurement, which is from 10Hz up to 10MHz for a typical LDO).

Fortunately, similar—and possibly lower—noise levels are achievable by stacking parallel op-amp stages, as discussed in the References [3] section. Therefore, select an op-amp with the lowest noise available to achieve a lower equivalent input voltage (EIVN) and equivalent input current noise (EICN), respectively. The selected op-amp must have a wide enough BW to accommodate the required gain over the noise measurement BW.

Texas Instruments offers plenty of low-noise op-amps. This design requires the lowest amount of noise and the widest amount of BW to accommodate the requirements of the design. Therefore, an op-amp with a noise level of 700pV/Hz to 950pV/Hz at 1kHz is a good potential candidate. Another required feature of the amplifier design is that the op-amp must have a very low 1/f noise level at 1kHz.

Using the parallel op-amp technique (discussed in the References [3] section) and an op-amp with roughly 800pV/Hz of noise results in roughly ten parallel stages, as shown in the Equation 2:

Equation 2. N u m b e r   o f   s t a g e s   ( N )   =   800 p V H z 250 p V H z 2 =   10 . 24

The results from simulation and prototyping found that ten stages maintains a margin of more than 10dB against parasitic and components tolerance without significantly complicating the circuit design of the amplifier.