SLVK086A january   2022  – may 2023 TPS7H4003-SEP

PRODUCTION DATA  

  1.   1
  2.   Single-Event Effects Test Report of the TPS7H4003-SEP Synchronous Step-Down Converter
  3.   Trademarks
  4. 1 Introduction
  5. 2 Single-Event Effects (SEE)
  6. 3 Device and Test Board Information
  7. 4 Irradiation Facility and Setup
  8. 5 Depth, Range, and LETEFF Calculation
  9. 6 Test Setup and Procedures
  10. 7 Destructive Single-Event Effects (DSEE)
    1. 7.1 Single-Event Latch-up (SEL) Results
    2. 7.2 Single-Event Burnout (SEB) and Single-Event Gate Rupture (SEGR) Results
  11. 8 Single-Event Transients (SET)
  12. 9 Event Rate Calculations
  13. 10Summary
  14.   A Appendix: Total Ionizing Dose From SEE Experiments
  15.   B Appendix: References
  16.   C Revision History

2 Single-Event Effects (SEE)

The primary concern for the TPS7H4003-SEP is the robustness against the destructive single-event effects (DSEE): single-event latch-up (SEL), single-event burnout (SEB), and single-event gate rupture (SEGR). In mixed technologies such as the BiCMOS process used on the TPS7H4003-SEP, the CMOS circuitry introduces a potential for SEL susceptibility.

SEL can occur if excess current injection caused by the passage of an energetic ion is high enough to trigger the formation of a parasitic cross-coupled PNP and NPN bipolar structure (formed between the p-sub and n-well and n+ and p+ contacts) [1,2]. The parasitic bipolar structure initiated by a single-event creates a high-conductance path (inducing a steady-state current that is typically orders-of-magnitude higher than the normal operating current) between power and ground that persists (is “latched”) until power is removed, the device is reset, or until the device is destroyed by the high-current state. The TPS7H4003-SEP was tested for SEL at the maximum recommended voltage of 7 V, maximum load current of 18 A, and VOUT of 1 V. The device exhibited no SEL when heavy-ions with LETEFF = 48.2 MeV·cm2/mg at flux ≈105 ions/cm2·s, fluence of ≈107 ions/cm2, and a die temperature of 125°C.

Since this device is designed to conduct large currents (up to 18 A) and withstand up to 7 V during the off-state, the power LDMOS introduces a potential susceptibility for SEB and SEGR [2]. The TPS7H4003-SEP was evaluated for SEB/SEGR at full load conditions of 18 A, and a maximum voltage of 7 V in both the enabled and disabled modes. All testing for SEB and SEGR was done at room temperature with no external heating or cooling implemented. During the SEB/SEGR testing, not a single current event was observed, demonstrating that the TPS7H4003-SEP is SEB/SEGR-free up to LETEFF = 48.2 MeV·cm2/mg at a flux of ≈105 ions/cm2·s, fluence of ≈107 ions/cm2.

The TPS7H4003-SEP was characterize for SET at flux of ≈105 ions/cm2·s, fluence of 1 × 107 ions/cm2, and room temperature. The device was characterized at PVIN = 5, 6, and 6.5 V to VOUT = 1 V at full load of 18-A load. Under these conditions the device showed one SET signature under heavy-ion irradiation. All observed types of SETs were self-recoverable without the need of external intervention. The SET signature occurred with test conditions of a ±3% window trigger on VOUT, a negative edge trigger on SS with a trigger value of 0.6 V, and a negative edge trigger on PGOOD with a trigger value of VIN – 0.5 V.