SLVUBI1 May   2021

 

  1.   Trademarks
  2. 1TPS7H4002EVM-CVAL Overview
    1. 1.1 Features
    2. 1.2 Applications
  3. 2TPS7H4002EVM-CVAL Default Configuration
  4. 3TPS7H4002EVM-CVAL Initial Setup
  5. 4TPS7H4002EVM-CVAL Testing
    1. 4.1 Output Voltage Regulation
    2. 4.2 Output Voltage Ripple
    3. 4.3 Soft Start-up
    4. 4.4 Transient Response to Positive/Negative Load Step (0 A to 3A to 0A)
    5. 4.5 Input Voltage Ripple
    6. 4.6 Loop Frequency Response
    7. 4.7 Current Limiting
  6. 5TPS7H4002EVM-CVAL EVM Schematic
  7. 6TPS7H4002EVM-CVAL Bill of Materials (BOM)
  8. 7Board Layout

2 TPS7H4002EVM-CVAL Default Configuration

Table 2-1 describes the default configuration of the TPS7H4002EVM-CVAL listing the external components that define the converter design.

Table 2-1 Default EVM Configuration
Parameter Specifications Description
Input power supply 5 V Bound by UVLO enable circuit (R13, R15)
Regulated output voltage

2.5 V

 R7 (RTOP) = 10 kΩ, R5 (RBOTTOM) = 4.7 kΩ
LOUT

2.2 µH

 Chosen to meet inductor ripple current of 40% (Kind = 0.4)
COUT 330 µF Chosen for (1) ESR = 6 mΩ to set output voltage ripple;
(2) value used during single event effects testing ensuring regulation maintained with single event upset to switching
Output current 0 to 3 A By design
Switching frequency 500 kHz Set by R10 (RT) = 95.3 kΩ
Soft start time constant ≈ 3.2 ms Set by C1 (Css) = 10 nF
UVLO enable rising ≈ 4.432 V Set by R13 = 10 kΩ and R15 = 3.4 kΩ
UVLO enable falling ≈ 4.284 V Set by R13 = 10 kΩ and R15 = 3.4 kΩ
Loop bandwidth ≈ 30 kHz Set by operational transconductance amplifier (OTA) compensation circuit: R14 (RCOMP) = 11.8 kΩ, C14 (CCOMP) = 22 nF, C6 (CHF) = 22 pF
Loop phase margin ≈ 60°
Gain margin ≈ –25 dB