SLVUCB3 March   2022

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Related Documentation
  3. 2Schematics, Bill of Materials, and Layout
    1. 2.1 TPS3760EVM Schematic
    2. 2.2 TPS3760EVM Bill of Materials
    3. 2.3 Layout and Component Placement
  4. 3EVM Connectors
    1. 3.1 EVM Test Points
    2. 3.2 EVM Jumpers
  5. 4EVM Setup and Operation
    1. 4.1 Input Power (VDD)
    2. 4.2 SENSE1/SENSE2 Inputs
    3. 4.3 RESET1/RESET2 Outputs
    4. 4.4 Capacitor Time Delay Reset/MR
    5. 4.5 Capacitor Time Delay Sense/MR

Capacitor Time Delay Reset/MR

The TPS3760 and TPS3760-Q1 family of devices contain two adjustable reset time delay pins that control the time with which the reset pins de-assert after they reach their valid condition. These pins also serve a dual purpose and act as a manual reset (MR) when connected to logic ground. The user can adjust the configuration of these pins via the jumpers located at J11 and J12. Header J11 serves as the selectable option for CTR1/MR and header J12 serves as the selectable option for CTR2/MR. Position DNI of the header (indicated by a DNI) connects the pin to a unstuffed 0603 capacitor pad for the user to solder on a capacitor of choice. The capacitor values for these jumpers are labeled on the board and are also listed in the jumper description section, and are as follows: for J11, from top to bottom, 10uF, 1uF, 100nF, 10nF, 1nF, DNI for a user specified value, and OPEN to be tied to GND for MR testing. For J12, from bottom to top, 10uF, 1uF, 100nF, 10nF, 1nF, DNI for a user specified value, and OPEN to be tied to GND for MR testing. Please see the adjustable Reset Time Delay Configuration on the TPS3760-Q1 datasheet for more detailed information on user programming.